| Line 57... |
Line 57... |
module ifetch(
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module ifetch(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// External i/f to IC
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// External i/f to IC
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ic_insn, ic_addr, ic_stall, ic_fetchop, tp_insn, tp_wr_insn,
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ic_insn, ic_addr, ic_stall, ic_fetchop,
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// Internal i/f
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// Internal i/f
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if_freeze, if_insn, if_pc, branch_op, except_type,
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if_freeze, if_insn, if_pc, branch_op, except_type,
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branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start,
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branch_addrofs, lr_restor, flag, taken, binsn_addr, except_start,
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epcr, force_dslot_fetch, if_stall, branch_stall
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epcr, force_dslot_fetch, if_stall, branch_stall
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| Line 82... |
Line 82... |
//
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//
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input [31:0] ic_insn;
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input [31:0] ic_insn;
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output [31:0] ic_addr;
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output [31:0] ic_addr;
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output [`FETCHOP_WIDTH-1:0] ic_fetchop;
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output [`FETCHOP_WIDTH-1:0] ic_fetchop;
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input ic_stall;
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input ic_stall;
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input [31:0] tp_insn;
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input tp_wr_insn;
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input if_freeze;
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input if_freeze;
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| Line 114... |
Line 112... |
reg [32:0] if_saved;
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reg [32:0] if_saved;
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reg [31:0] pcaddr;
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reg [31:0] pcaddr;
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reg [31:0] pc_saved;
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reg [31:0] pc_saved;
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reg taken; /* Set to in case of jump or taken branch */
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reg taken; /* Set to in case of jump or taken branch */
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// Selection between insn from IC or Trace port
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wire [31:0] ic_tp_insn = (tp_wr_insn) ? tp_insn : ic_insn;
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//
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//
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// Current registered PC (corresponds to fetched instruction)
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// Current registered PC (corresponds to fetched instruction)
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//
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//
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//assign if_pc = {pcreg[31:2], 2'b00};
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//assign if_pc = {pcreg[31:2], 2'b00};
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assign if_pc = (if_saved[32]) ? pc_saved : ic_addr;
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assign if_pc = (if_saved[32]) ? pc_saved : ic_addr;
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Line 130... |
assign ic_fetchop = (if_saved[32] & !if_stall) ? `FETCHOP_NOP : `FETCHOP_LW;
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assign ic_fetchop = (if_saved[32] & !if_stall) ? `FETCHOP_NOP : `FETCHOP_LW;
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//
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//
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// Just fetched instruction
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// Just fetched instruction
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//
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//
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assign if_insn = (if_saved[32]) ? if_saved[31:0] : (ic_stall) ? 32'h1500FFFF : ic_tp_insn;
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assign if_insn = (if_saved[32]) ? if_saved[31:0] : (ic_stall) ? 32'h1500FFFF : ic_insn;
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//
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//
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// Delay slot PC saved
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// Delay slot PC saved
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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Line 233... |
`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("Starting exception: %h.", except_type);
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$display("Starting exception: %h.", except_type);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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pcaddr = { 21'h0, except_type, 8'h00};
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pcaddr = { 20'h0_0000, except_type, 8'h00};
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taken = 1'b1;
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taken = 1'b1;
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end
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end
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endcase
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endcase
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end
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end
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| Line 268... |
Line 263... |
always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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if_saved <= #1 33'b0;
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if_saved <= #1 33'b0;
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end
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end
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else if (if_freeze && !if_saved[32] && !ic_stall) begin // && !taken
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else if (if_freeze && !if_saved[32] && !ic_stall) begin // && !taken
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if_saved <= #1 {1'b1, ic_tp_insn};
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if_saved <= #1 {1'b1, ic_insn};
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: if_saved <= %h", $time, {1'b1, ic_tp_insn});
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$display("%t: if_saved <= %h", $time, {1'b1, ic_insn});
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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end
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end
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else if (!if_freeze) begin
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else if (!if_freeze) begin
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if_saved[32] <= #1 1'b0;
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if_saved[32] <= #1 1'b0;
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