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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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`include "general.h"
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`include "timescale.v"
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`include "defines.v"
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module lsu(clk, rst, addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall,
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module lsu(
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dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop);
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// Clock and reset
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clk, rst,
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// Internal i/f
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addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall,
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// External i/f to DC
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dc_stall, dc_addr, dc_datain, dc_dataout, dc_lsuop
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);
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parameter dw = `OPERAND_WIDTH;
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parameter dw = `OPERAND_WIDTH;
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parameter aw = `REGFILE_ADDR_WIDTH;
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parameter aw = `REGFILE_ADDR_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input clk;
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input clk;
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input rst;
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input rst;
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//
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// Internal i/f
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//
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input [31:0] addrbase;
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input [31:0] addrbase;
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input [31:0] addrofs;
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input [31:0] addrofs;
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input [`LSUOP_WIDTH-1:0] lsu_op;
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input [`LSUOP_WIDTH-1:0] lsu_op;
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input [dw-1:0] lsu_datain;
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input [dw-1:0] lsu_datain;
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output [dw-1:0] lsu_dataout;
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output [dw-1:0] lsu_dataout;
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output lsu_stall;
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output lsu_stall;
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//
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// External i/f to DC
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//
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input dc_stall;
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input dc_stall;
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output [31:0] dc_addr;
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output [31:0] dc_addr;
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input [dw-1:0] dc_datain;
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input [dw-1:0] dc_datain;
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output [dw-1:0] dc_dataout;
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output [dw-1:0] dc_dataout;
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output [`LSUOP_WIDTH-1:0] dc_lsuop;
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output [`LSUOP_WIDTH-1:0] dc_lsuop;
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//
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// Not much of a LSU right now
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//
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assign dc_addr = addrbase + addrofs;
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assign dc_addr = addrbase + addrofs;
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assign dc_dataout = lsu_datain;
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assign dc_dataout = lsu_datain;
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assign lsu_dataout = dc_datain;
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assign lsu_dataout = dc_datain;
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assign lsu_stall = dc_stall;
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assign lsu_stall = dc_stall;
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assign dc_lsuop = lsu_op;
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assign dc_lsuop = lsu_op;
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