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Rev 161 Rev 168
Line 42... Line 42... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
//
 
//
 
// CVS Revision History
 
// CVS Revision History
 
//
 
//
 
// $Log: not supported by cvs2svn $
 
// $Log: not supported by cvs2svn $
 
 
 
// Revision 1.1  2001/07/20 00:46:03  lampret
 
 
 
// Development version of RTL. Libraries are missing.
 
 
 
//
 
//
 
//
 
 
 
 
 
`include "general.h"
 
`include "timescale.v"
 
 
 
`include "defines.v"
 
 
 
 
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
module mem2reg(addr, lsu_op, memdata, regdata);
 
 
 
 
 
parameter width = `OPERAND_WIDTH;
 
parameter width = `OPERAND_WIDTH;
 
 
 
 
 
 
 
//
 
 
 
// I/O
 
 
 
//
 
input [1:0] addr;
 
input [1:0] addr;
 
input [`LSUOP_WIDTH-1:0] lsu_op;
 
input [`LSUOP_WIDTH-1:0] lsu_op;
 
input [width-1:0] memdata;
 
input [width-1:0] memdata;
 
 
 
 
 
output [width-1:0] regdata;
 
output [width-1:0] regdata;
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Faster implementation of mem2reg
 
 
 
//
 
`ifdef MEM2REG_FAST
 
`ifdef MEM2REG_FAST
 
 
 
 
 
`define SEL_00 2'b00
 
`define SEL_00 2'b00
 
`define SEL_01 2'b01
 
`define SEL_01 2'b01
 
`define SEL_10 2'b10
 
`define SEL_10 2'b10
 
`define SEL_11 2'b11
 
`define SEL_11 2'b11
 
 
 
 
 
reg [width-1:0] regdata;
 
reg [width-1:0] regdata;
 
reg [width-1:0] aligned;
 
reg [width-1:0] aligned;
 
reg [1:0] sel_byte0, sel_byte1, sel_byte2, sel_byte3;
 
reg     [1:0]                    sel_byte0, sel_byte1,
 
 
 
                                sel_byte2, sel_byte3;
 
 
 
 
 
 
 
//
 
 
 
// Byte select 0
 
 
 
//
 
always @(addr or lsu_op) begin
 
always @(addr or lsu_op) begin
 
        casex({lsu_op[2:0], addr})
 
        casex({lsu_op[2:0], addr})
 
                {3'b01x, 2'b00}:
 
                {3'b01x, 2'b00}:
 
                        sel_byte0 <= #1 `SEL_11;
 
                        sel_byte0 <= #1 `SEL_11;
 
                {3'b01x, 2'b01}:
 
                {3'b01x, 2'b01}:
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                default:
 
                default:
 
                        sel_byte0 <= #1 `SEL_00;
 
                        sel_byte0 <= #1 `SEL_00;
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte select 1
 
 
 
//
 
always @(addr or lsu_op) begin
 
always @(addr or lsu_op) begin
 
        casex({lsu_op[2:0], addr})
 
        casex({lsu_op[2:0], addr})
 
                {3'b010, 2'bxx}:
 
                {3'b010, 2'bxx}:
 
                        sel_byte1 <= #1 `SEL_00;        // zero extend
 
                        sel_byte1 <= #1 `SEL_00;        // zero extend
 
                {3'b011, 2'bxx}:
 
                {3'b011, 2'bxx}:
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                default:
 
                default:
 
                        sel_byte1 <= #1 `SEL_01;
 
                        sel_byte1 <= #1 `SEL_01;
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte select 2
 
 
 
//
 
always @(addr or lsu_op) begin
 
always @(addr or lsu_op) begin
 
        casex({lsu_op[2:0], addr})
 
        casex({lsu_op[2:0], addr})
 
                {3'b010, 2'bxx},
 
                {3'b010, 2'bxx},
 
                {3'b100, 2'bxx}:
 
                {3'b100, 2'bxx}:
 
                        sel_byte2 <= #1 `SEL_00;        // zero extend
 
                        sel_byte2 <= #1 `SEL_00;        // zero extend
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                default:
 
                default:
 
                        sel_byte2 <= #1 `SEL_10;
 
                        sel_byte2 <= #1 `SEL_10;
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte select 3
 
 
 
//
 
always @(addr or lsu_op) begin
 
always @(addr or lsu_op) begin
 
        casex({lsu_op[2:0], addr})
 
        casex({lsu_op[2:0], addr})
 
                {3'b010, 2'bxx},
 
                {3'b010, 2'bxx},
 
                {3'b100, 2'bxx}:
 
                {3'b100, 2'bxx}:
 
                        sel_byte3 <= #1 `SEL_00;        // zero extend
 
                        sel_byte3 <= #1 `SEL_00;        // zero extend
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                default:
 
                default:
 
                        sel_byte3 <= #1 `SEL_11;
 
                        sel_byte3 <= #1 `SEL_11;
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte 0
 
 
 
//
 
always @(sel_byte0 or memdata) begin
 
always @(sel_byte0 or memdata) begin
 
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
 
        case(sel_byte0) // synopsys full_case parallel_case infer_mux
 
                `SEL_00: begin
 
                `SEL_00: begin
 
                                regdata[7:0] <= #1 memdata[7:0];
 
                                regdata[7:0] <= #1 memdata[7:0];
 
                        end
 
                        end
Line 144... Line 170... 
                                regdata[7:0] <= #1 memdata[31:24];
 
                                regdata[7:0] <= #1 memdata[31:24];
 
                        end
 
                        end
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte 1
 
 
 
//
 
always @(sel_byte1 or memdata) begin
 
always @(sel_byte1 or memdata) begin
 
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
 
        case(sel_byte1) // synopsys full_case parallel_case infer_mux
 
                `SEL_00: begin
 
                `SEL_00: begin
 
                                regdata[15:8] <= #1 8'b0;
 
                                regdata[15:8] <= #1 8'b0;
 
                        end
 
                        end
Line 161... Line 190... 
                                regdata[15:8] <= #1 memdata[31:24];
 
                                regdata[15:8] <= #1 memdata[31:24];
 
                        end
 
                        end
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte 2
 
 
 
//
 
always @(sel_byte2 or memdata) begin
 
always @(sel_byte2 or memdata) begin
 
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
 
        case(sel_byte2) // synopsys full_case parallel_case infer_mux
 
                `SEL_00: begin
 
                `SEL_00: begin
 
                                regdata[23:16] <= #1 8'b0;
 
                                regdata[23:16] <= #1 8'b0;
 
                        end
 
                        end
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                                regdata[23:16] <= #1 {8{memdata[15]}};
 
                                regdata[23:16] <= #1 {8{memdata[15]}};
 
                        end
 
                        end
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Byte 3
 
 
 
//
 
always @(sel_byte3 or memdata) begin
 
always @(sel_byte3 or memdata) begin
 
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
 
        case(sel_byte3) // synopsys full_case parallel_case infer_mux
 
                `SEL_00: begin
 
                `SEL_00: begin
 
                                regdata[31:24] <= #1 8'b0;
 
                                regdata[31:24] <= #1 8'b0;
 
                        end
 
                        end
Line 197... Line 232... 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
`else
 
`else
 
 
 
 
 
 
 
//
 
 
 
// Slow implementation of mem2reg
 
 
 
//
 
 
 
 
 
reg [width-1:0] regdata;
 
reg [width-1:0] regdata;
 
reg [width-1:0] aligned;
 
reg [width-1:0] aligned;
 
 
 
 
 
 
 
//
 
 
 
// Alignment
 
 
 
//
 
always @(addr or memdata) begin
 
always @(addr or memdata) begin
 
        case(addr) // synopsys infer_mux
 
        case(addr) // synopsys infer_mux
 
                2'b00:
 
                2'b00:
 
                        aligned <= #1 memdata;
 
                        aligned <= #1 memdata;
 
                2'b01:
 
                2'b01:
Line 213... Line 255... 
                2'b11:
 
                2'b11:
 
                        aligned <= #1 {memdata[7:0], 24'b0};
 
                        aligned <= #1 {memdata[7:0], 24'b0};
 
        endcase
 
        endcase
 
end
 
end
 
 
 
 
 
 
 
//
 
 
 
// Bytes
 
 
 
//
 
always @(lsu_op or aligned) begin
 
always @(lsu_op or aligned) begin
 
//      $display("mem2reg: memdata=%h", memdata);
 
 
 
        case(lsu_op) // synopsys infer_mux
 
        case(lsu_op) // synopsys infer_mux
 
                `LSUOP_LBZ: begin
 
                `LSUOP_LBZ: begin
 
                                regdata[7:0] <= #1 aligned[31:24];
 
                                regdata[7:0] <= #1 aligned[31:24];
 
                                regdata[31:8] <= #1 24'b0;
 
                                regdata[31:8] <= #1 24'b0;
 
                        end
 
                        end

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