URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Diff between revs 161 and 166

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Rev 161	Rev 166
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/07/20 00:46:21 lampret`
	`// Development version of RTL. Libraries are missing.`
	`//`
`//`	`//`

`include "general.h"	`include "general.h"

`module or1200(`	`module or1200(`
Line 129...	Line 132...
`wire [dw-1:0] dcbiu_from_biu;`	`wire [dw-1:0] dcbiu_from_biu;`
`wire [dw-1:0] dcbiu_to_biu;`	`wire [dw-1:0] dcbiu_to_biu;`
`wire [aw-1:0] dcbiu_addr;`	`wire [aw-1:0] dcbiu_addr;`
`wire dcbiu_read;`	`wire dcbiu_read;`
`wire dcbiu_write;`	`wire dcbiu_write;`
	`wire [3:0] dcbiu_sel;`

`// IC to BIU`	`// IC to BIU`
`wire icbiu_rdy;`	`wire icbiu_rdy;`
`wire [dw-1:0] icbiu_from_biu;`	`wire [dw-1:0] icbiu_from_biu;`
`wire [aw-1:0] icbiu_addr;`	`wire [aw-1:0] icbiu_addr;`
Line 209...	Line 213...
`.biu_to_biu(32'b0),`	`.biu_to_biu(32'b0),`
`.biu_addr(icbiu_addr),`	`.biu_addr(icbiu_addr),`
`.biu_read(icbiu_read),`	`.biu_read(icbiu_read),`
`.biu_write(1'b0),`	`.biu_write(1'b0),`
`.biu_rdy(icbiu_rdy),`	`.biu_rdy(icbiu_rdy),`
`.biu_from_biu(icbiu_from_biu)`	`.biu_from_biu(icbiu_from_biu),`
	`.biu_sel(4'b1111)`
`);`	`);`

`//`	`//`
`// Instantiation of Data WISHBONE BIU`	`// Instantiation of Data WISHBONE BIU`
`//`	`//`
Line 236...	Line 241...
`.biu_to_biu(dcbiu_to_biu),`	`.biu_to_biu(dcbiu_to_biu),`
`.biu_addr(dcbiu_addr),`	`.biu_addr(dcbiu_addr),`
`.biu_read(dcbiu_read),`	`.biu_read(dcbiu_read),`
`.biu_write(dcbiu_write),`	`.biu_write(dcbiu_write),`
`.biu_rdy(dcbiu_rdy),`	`.biu_rdy(dcbiu_rdy),`
`.biu_from_biu(dcbiu_from_biu)`	`.biu_from_biu(dcbiu_from_biu),`
	`.biu_sel(dcbiu_sel)`
`);`	`);`

`//`	`//`
`// Instantiation of Instruction Cache`	`// Instantiation of Instruction Cache`
`//`	`//`
Line 334...	Line 340...
`.dcbiu_datain(dcbiu_from_biu),`	`.dcbiu_datain(dcbiu_from_biu),`
`.dcbiu_dataout(dcbiu_to_biu),`	`.dcbiu_dataout(dcbiu_to_biu),`
`.dcbiu_addr(dcbiu_addr),`	`.dcbiu_addr(dcbiu_addr),`
`.dcbiu_read(dcbiu_read),`	`.dcbiu_read(dcbiu_read),`
`.dcbiu_write(dcbiu_write),`	`.dcbiu_write(dcbiu_write),`
	`.dcbiu_sel(dcbiu_sel),`

`// Trace port`	`// Trace port`
`.tp2w(tp2w),`	`.tp2w(tp2w),`
`.tp3w(tp3w),`	`.tp3w(tp3w),`
`.tpdw(tpdw)`	`.tpdw(tpdw)`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Diff between revs 161 and 166