Subversion Repositories or1k

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//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.1  2001/07/20 00:46:21  lampret

// Revision 1.1  2001/07/20 00:46:21  lampret

// Development version of RTL. Libraries are missing.

// Development version of RTL. Libraries are missing.

//

//

//

//

module or1200(

module or1200(

        clk, rst, pic_ints, clkdiv_by_2,

        clk, rst, pic_ints, clkdiv_by_2,

        // Instruction WISHBONE INTERFACE

        // Instruction WISHBONE INTERFACE

        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,

        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,

        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,

        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,

parameter dw = `OPERAND_WIDTH;

parameter dw = `OPERAND_WIDTH;

parameter aw = `OPERAND_WIDTH;

parameter aw = `OPERAND_WIDTH;

parameter ppic_ints = `PIC_INTS;

parameter ppic_ints = `PIC_INTS;

//

//

// Instruction WISHBONE interface

// Instruction WISHBONE interface

//

//

input                   iwb_clk_i;      // clock input

input                   iwb_clk_i;      // clock input

input                   iwb_rst_i;      // reset input

input                   iwb_rst_i;      // reset input

input                   iwb_ack_i;      // normal termination

input                   iwb_ack_i;      // normal termination

output                  dwb_we_o;       // indicates write transfer

output                  dwb_we_o;       // indicates write transfer

output [3:0]             dwb_sel_o;      // byte select outputs

output [3:0]             dwb_sel_o;      // byte select outputs

output [dw-1:0]          dwb_dat_o;      // output data bus

output [dw-1:0]          dwb_dat_o;      // output data bus

//

//

//

//

input                   pm_cpustall;

input                   pm_cpustall;

output                  pm_clksd;

output                  pm_clksd;

output                  pm_dc_gate;

output                  pm_dc_gate;

output                  pm_ic_gate;

output                  pm_ic_gate;

output                  pm_dmmu_gate;

output                  pm_dmmu_gate;

output                  pm_tt_gate;

output                  pm_tt_gate;

output                  pm_cpu_gate;

output                  pm_cpu_gate;

output                  pm_wakeup;

output                  pm_wakeup;

output                  pm_lvolt;

output                  pm_lvolt;

// DC to BIU

// DC to BIU

wire                    dcbiu_rdy;

wire                    dcbiu_rdy;

wire [dw-1:0]            dcbiu_from_biu;

wire [dw-1:0]            dcbiu_from_biu;

wire [dw-1:0]            dcbiu_to_biu;

wire [dw-1:0]            dcbiu_to_biu;

wire [aw-1:0]            dcbiu_addr;

wire [aw-1:0]            dcbiu_addr;

wire                    dcbiu_read;

wire                    dcbiu_read;

wire                    dcbiu_write;

wire                    dcbiu_write;

wire [3:0]               dcbiu_sel;

wire [3:0]               dcbiu_sel;

// IC to BIU

// IC to BIU

wire                    icbiu_rdy;

wire                    icbiu_rdy;

wire [dw-1:0]            icbiu_from_biu;

wire [dw-1:0]            icbiu_from_biu;

wire [aw-1:0]            icbiu_addr;

wire [aw-1:0]            icbiu_addr;

wire                    icbiu_read;

wire                    icbiu_read;

// CPU's SPR access to various RISC units (shared wires)

// CPU's SPR access to various RISC units (shared wires)

wire [aw-1:0]            spr_addr;

wire [aw-1:0]            spr_addr;

wire [dw-1:0]            spr_dat_cpu;

wire [dw-1:0]            spr_dat_cpu;

wire [31:0]              spr_cs;

wire [31:0]              spr_cs;

wire                    spr_we;

wire                    spr_we;

// DC and CPU's LSU

// DC and CPU's LSU

wire                    dclsu_stall;

wire                    dclsu_stall;

wire [aw-1:0]            dclsu_addr;

wire [aw-1:0]            dclsu_addr;

wire [aw-1:0]            dclsu_from_dc;

wire [aw-1:0]            dclsu_from_dc;

wire [aw-1:0]            dclsu_to_dc;

wire [aw-1:0]            dclsu_to_dc;

wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;

wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;

// IC and CPU's ifetch

// IC and CPU's ifetch

wire                    icfetch_stall;

wire                    icfetch_stall;

wire [aw-1:0]            icfetch_addr;

wire [aw-1:0]            icfetch_addr;

wire [dw-1:0]            icfetch_dataout;

wire [dw-1:0]            icfetch_dataout;

// Connection between CPU and PIC

// Connection between CPU and PIC

wire [dw-1:0]            spr_dat_pic;

wire [dw-1:0]            spr_dat_pic;

wire                    pic_wakeup;

wire                    pic_wakeup;

wire                    int_low;

wire                    int_low;

wire                    int_high;

wire                    int_high;

wire                    int_high_tt;

wire                    int_high_tt;

// Connection between CPU and PM

// Connection between CPU and PM

wire [dw-1:0]            spr_dat_pm;

wire [dw-1:0]            spr_dat_pm;

// CPU and TT

// CPU and TT

wire [dw-1:0]            spr_dat_tt;

wire [dw-1:0]            spr_dat_tt;

wire                    tt_int;

wire                    tt_int;

// CPU and external Trace port

// CPU and external Trace port

input                   tp_dir_in;

input                   tp_dir_in;

input [1:0]              tp_sel;

input [1:0]              tp_sel;

input [dw-1:0]           tp_in;

input [dw-1:0]           tp_in;

output [dw-1:0]          tp_out;

output [dw-1:0]          tp_out;

// Trace port and caches/MMUs

// Trace port and caches/MMUs

wire [`TP2W_WIDTH-1:0]   tp2w;

wire [`TP2W_WIDTH-1:0]   tp2w;

wire [`TP3W_WIDTH-1:0]   tp3w;

wire [`TP3W_WIDTH-1:0]   tp3w;

//

//

// Assignments

// Assignments

//

//

assign int_high_tt = int_high | tt_int;

assign int_high_tt = int_high | tt_int;

        .icbiu_datain(icbiu_from_biu),

        .icbiu_datain(icbiu_from_biu),

        .icbiu_addr(icbiu_addr),

        .icbiu_addr(icbiu_addr),

        .icbiu_read(icbiu_read),

        .icbiu_read(icbiu_read),

        // These connect IC to SPRS

        // These connect IC to SPRS

);

);

//

//

// Instantiation of Instruction Cache

// Instantiation of Instruction Cache

//

//

        .dclsu_stall(dclsu_stall),

        .dclsu_stall(dclsu_stall),

        .dclsu_addr(dclsu_addr),

        .dclsu_addr(dclsu_addr),

        .dclsu_datain(dclsu_from_dc),

        .dclsu_datain(dclsu_from_dc),

        .dclsu_dataout(dclsu_to_dc),

        .dclsu_dataout(dclsu_to_dc),

        .dclsu_lsuop(dclsu_lsuop),

        .dclsu_lsuop(dclsu_lsuop),

        // These connect PIC and CPU's EXCEPT

        // These connect PIC and CPU's EXCEPT

        .int_high(int_high_tt),

        .int_high(int_high_tt),

        .int_low(int_low),

        .int_low(int_low),

        .spr_cs(spr_cs),

        .spr_cs(spr_cs),

        .spr_we(spr_we),

        .spr_we(spr_we),

        // These connect trace port to caches and MMUs

        // These connect trace port to caches and MMUs

        .tp2w(tp2w),

        .tp2w(tp2w),

);

);

//

//

// Instantiation of Data Cache

// Instantiation of Data Cache

//

//

        .dclsu_addr(dclsu_addr),

        .dclsu_addr(dclsu_addr),

        .dclsu_lsuop(dclsu_lsuop),

        .dclsu_lsuop(dclsu_lsuop),

        .dclsu_datain(dclsu_to_dc),

        .dclsu_datain(dclsu_to_dc),

        .dclsu_dataout(dclsu_from_dc),

        .dclsu_dataout(dclsu_from_dc),

        .dclsu_stall(dclsu_stall),

        .dclsu_stall(dclsu_stall),

        // These connect DC to BIU

        // These connect DC to BIU

        .dcbiu_rdy(dcbiu_rdy),

        .dcbiu_rdy(dcbiu_rdy),

        .dcbiu_datain(dcbiu_from_biu),

        .dcbiu_datain(dcbiu_from_biu),

        .dcbiu_dataout(dcbiu_to_biu),

        .dcbiu_dataout(dcbiu_to_biu),

        .dcbiu_read(dcbiu_read),

        .dcbiu_read(dcbiu_read),

        .dcbiu_write(dcbiu_write),

        .dcbiu_write(dcbiu_write),

        .dcbiu_sel(dcbiu_sel),

        .dcbiu_sel(dcbiu_sel),

        // Trace port

        // Trace port

);

);

//

//

// Programmable interrupt controller

// Programmable interrupt controller

//

//

);

);

endmodule

endmodule

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