| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/08/09 13:39:33 lampret
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|
// Major clean-up.
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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| Line 158... |
Line 161... |
//
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//
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wire icbiu_rdy;
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wire icbiu_rdy;
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wire [dw-1:0] icbiu_from_biu;
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wire [dw-1:0] icbiu_from_biu;
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wire [aw-1:0] icbiu_addr;
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wire [aw-1:0] icbiu_addr;
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wire icbiu_read;
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wire icbiu_read;
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wire [3:0] icbiu_sel;
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|
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//
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//
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// CPU's SPR access to various RISC units (shared wires)
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// CPU's SPR access to various RISC units (shared wires)
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//
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//
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wire [aw-1:0] spr_addr;
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wire [aw-1:0] spr_addr;
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| Line 183... |
Line 187... |
// IC and CPU's ifetch
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// IC and CPU's ifetch
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//
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//
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wire icfetch_stall;
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wire icfetch_stall;
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wire [aw-1:0] icfetch_addr;
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wire [aw-1:0] icfetch_addr;
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wire [dw-1:0] icfetch_dataout;
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wire [dw-1:0] icfetch_dataout;
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|
wire ic_en;
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|
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//
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//
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// Connection between CPU and PIC
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// Connection between CPU and PIC
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//
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//
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wire [dw-1:0] spr_dat_pic;
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wire [dw-1:0] spr_dat_pic;
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| Line 248... |
Line 253... |
.biu_addr(icbiu_addr),
|
.biu_addr(icbiu_addr),
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.biu_read(icbiu_read),
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.biu_read(icbiu_read),
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.biu_write(1'b0),
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.biu_write(1'b0),
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.biu_rdy(icbiu_rdy),
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.biu_rdy(icbiu_rdy),
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.biu_from_biu(icbiu_from_biu),
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.biu_from_biu(icbiu_from_biu),
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.biu_sel(4'b1111)
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.biu_sel(icbiu_sel)
|
);
|
);
|
|
|
//
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//
|
// Instantiation of Data WISHBONE BIU
|
// Instantiation of Data WISHBONE BIU
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//
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//
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| Line 292... |
Line 297... |
// These connect IC to CPU's ifetch
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// These connect IC to CPU's ifetch
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.icfetch_addr(icfetch_addr),
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.icfetch_addr(icfetch_addr),
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.icfetch_op(`FETCHOP_LW),
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.icfetch_op(`FETCHOP_LW),
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.icfetch_dataout(icfetch_dataout),
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.icfetch_dataout(icfetch_dataout),
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.icfetch_stall(icfetch_stall),
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.icfetch_stall(icfetch_stall),
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.ic_en(ic_en),
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|
|
// These connect IC to BIU
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// These connect IC to BIU
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.icbiu_rdy(icbiu_rdy),
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.icbiu_rdy(icbiu_rdy),
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.icbiu_datain(icbiu_from_biu),
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.icbiu_datain(icbiu_from_biu),
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.icbiu_addr(icbiu_addr),
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.icbiu_addr(icbiu_addr),
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.icbiu_read(icbiu_read),
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.icbiu_read(icbiu_read),
|
|
.icbiu_sel(icbiu_sel),
|
|
|
// These connect IC to SPRS
|
// These connect IC to SPRS
|
.spr_dat_i(spr_dat_cpu)
|
.spr_dat_i(spr_dat_cpu)
|
);
|
);
|
|
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| Line 314... |
Line 321... |
|
|
// These connect IC and IFETCHER inside CPU
|
// These connect IC and IFETCHER inside CPU
|
.ic_insn(icfetch_dataout),
|
.ic_insn(icfetch_dataout),
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.ic_pcaddr(icfetch_addr),
|
.ic_pcaddr(icfetch_addr),
|
.ic_stall(icfetch_stall),
|
.ic_stall(icfetch_stall),
|
|
.ic_en(ic_en),
|
|
|
// These connect CPU to external Trace port
|
// These connect CPU to external Trace port
|
.tp_dir_in(tp_dir_in),
|
.tp_dir_in(tp_dir_in),
|
.tp_sel(tp_sel),
|
.tp_sel(tp_sel),
|
.tp_in(tp_in),
|
.tp_in(tp_in),
|
