| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/08/13 03:36:20 lampret
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// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
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//
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Revision 1.3 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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//
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//
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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// Fixed RAM's oen bug. Cache bypass under development.
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| Line 53... |
Line 56... |
// Revision 1.1 2001/07/20 00:46:21 lampret
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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`include "defines.v"
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module or1200(
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module or1200(
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// System
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// System
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clk, rst, pic_ints, clkdiv_by_2,
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clk, rst, pic_ints, clkdiv_by_2,
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| Line 166... |
Line 171... |
wire [3:0] icbiu_sel;
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wire [3:0] icbiu_sel;
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//
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//
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// CPU's SPR access to various RISC units (shared wires)
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// CPU's SPR access to various RISC units (shared wires)
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//
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//
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wire supv;
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wire [aw-1:0] spr_addr;
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wire [aw-1:0] spr_addr;
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wire [dw-1:0] spr_dat_cpu;
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wire [dw-1:0] spr_dat_cpu;
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wire [31:0] spr_cs;
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wire [31:0] spr_cs;
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wire spr_we;
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wire spr_we;
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//
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//
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// DMMU and CPU
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//
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wire dmmu_en;
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wire dmmuexcept_miss;
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wire dmmuexcept_fault;
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wire [31:0] spr_dat_dmmu;
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//
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// DMMU and DC
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//
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wire [aw-1:0] dcdmmu_paddr;
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//
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// DC and CPU's LSU
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// DC and CPU's LSU
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//
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//
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wire dclsu_stall;
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wire dclsu_stall;
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wire dclsu_unstall;
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wire [aw-1:0] dclsu_addr;
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wire [aw-1:0] dclsu_addr;
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wire [aw-1:0] dclsu_from_dc;
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wire [aw-1:0] dclsu_from_dc;
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wire [aw-1:0] dclsu_to_dc;
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wire [aw-1:0] dclsu_to_dc;
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wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
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wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
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wire dc_en;
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wire dc_en;
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//
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//
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// IMMU and CPU
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//
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wire immu_en;
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wire immuexcept_miss;
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wire immuexcept_fault;
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wire [31:0] spr_dat_immu;
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//
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// IC and CPU's ifetch
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// IC and CPU's ifetch
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//
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//
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wire icfetch_stall;
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wire icfetch_stall;
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wire [aw-1:0] icfetch_addr;
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wire [aw-1:0] icfetch_addr;
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wire [dw-1:0] icfetch_dataout;
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wire [dw-1:0] icfetch_dataout;
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wire [`FETCHOP_WIDTH-1:0] icfetch_op;
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wire ic_en;
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wire ic_en;
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//
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//
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// IMMU and IC
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//
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wire [aw-1:0] icimmu_paddr;
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//
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// Connection between CPU and PIC
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// Connection between CPU and PIC
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//
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//
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wire [dw-1:0] spr_dat_pic;
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wire [dw-1:0] spr_dat_pic;
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wire pic_wakeup;
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wire pic_wakeup;
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wire int_low;
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wire int_low;
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| Line 285... |
Line 319... |
.biu_from_biu(dcbiu_from_biu),
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.biu_from_biu(dcbiu_from_biu),
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.biu_sel(dcbiu_sel)
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.biu_sel(dcbiu_sel)
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);
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);
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//
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//
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// Instantiation of IMMU
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//
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immu immu(
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// Rst and clk
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.clk(clk),
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.rst(rst),
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// Fetch i/f
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.immu_en(immu_en),
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.supv(supv),
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.immufetch_vaddr(icfetch_addr),
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.immufetch_op(icfetch_op),
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.immufetch_stall(),
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// Except I/F
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.immuexcept_miss(immuexcept_miss),
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.immuexcept_fault(immuexcept_fault),
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// SPR access
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.spr_cs(spr_cs[`SPR_GROUP_IMMU]),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_immu),
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// IC i/f
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.icimmu_paddr(icimmu_paddr)
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);
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//
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// Instantiation of Instruction Cache
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// Instantiation of Instruction Cache
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//
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//
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ic ic(
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ic ic(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.clkdiv_by_2(clkdiv_by_2),
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.clkdiv_by_2(clkdiv_by_2),
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// These connect IC to CPU's ifetch
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// These connect IC to CPU's ifetch
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.icfetch_addr(icfetch_addr),
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.icfetch_addr(icimmu_paddr),
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.icfetch_op(`FETCHOP_LW),
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.icfetch_op(icfetch_op),
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.icfetch_dataout(icfetch_dataout),
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.icfetch_dataout(icfetch_dataout),
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.icfetch_stall(icfetch_stall),
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.icfetch_stall(icfetch_stall),
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.ic_en(ic_en),
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.ic_en(ic_en),
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// These connect IC to BIU
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// These connect IC to BIU
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| Line 317... |
Line 381... |
//
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//
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cpu cpu(
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cpu cpu(
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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// These connect IC and IFETCHER inside CPU
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// Connection IC and IFETCHER inside CPU
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.ic_insn(icfetch_dataout),
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.ic_insn(icfetch_dataout),
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.ic_pcaddr(icfetch_addr),
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.ic_addr(icfetch_addr),
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.ic_stall(icfetch_stall),
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.ic_stall(icfetch_stall),
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.ic_fetchop(icfetch_op),
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.ic_en(ic_en),
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.ic_en(ic_en),
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// These connect CPU to external Trace port
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// Connection CPU to external Trace port
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.tp_dir_in(tp_dir_in),
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.tp_dir_in(tp_dir_in),
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.tp_sel(tp_sel),
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.tp_sel(tp_sel),
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.tp_in(tp_in),
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.tp_in(tp_in),
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.tp_out(tp_out),
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.tp_out(tp_out),
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// These connect DC and CPU's LSU
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// Connection IMMU and CPU internally
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.immu_en(immu_en),
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.immuexcept_miss(immuexcept_miss),
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.immuexcept_fault(immuexcept_fault),
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// Connection DMMU and CPU internally
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.dmmu_en(dmmu_en),
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.dmmuexcept_miss(dmmuexcept_miss),
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.dmmuexcept_fault(dmmuexcept_fault),
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// Connection DC and CPU's LSU
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.dclsu_stall(dclsu_stall),
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.dclsu_stall(dclsu_stall),
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.dclsu_unstall(dclsu_unstall),
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.dclsu_addr(dclsu_addr),
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.dclsu_addr(dclsu_addr),
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.dclsu_datain(dclsu_from_dc),
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.dclsu_datain(dclsu_from_dc),
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.dclsu_dataout(dclsu_to_dc),
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.dclsu_dataout(dclsu_to_dc),
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.dclsu_lsuop(dclsu_lsuop),
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.dclsu_lsuop(dclsu_lsuop),
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.dc_en(dc_en),
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.dc_en(dc_en),
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// These connect PIC and CPU's EXCEPT
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// Connection PIC and CPU's EXCEPT
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.int_high(int_high_tt),
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.int_high(int_high_tt),
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.int_low(int_low),
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.int_low(int_low),
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// SPRs
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// SPRs
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.supv(supv),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dataout(spr_dat_cpu),
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.spr_dataout(spr_dat_cpu),
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.spr_dat_pic(spr_dat_pic),
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.spr_dat_pic(spr_dat_pic),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_tt(spr_dat_tt),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_pm(spr_dat_pm),
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.spr_dat_dmmu(spr_dat_dmmu),
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.spr_cs(spr_cs),
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.spr_cs(spr_cs),
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.spr_we(spr_we),
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.spr_we(spr_we),
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// These connect trace port to caches and MMUs
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// These connect trace port to caches and MMUs
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.tp2w(tp2w),
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.tp2w(tp2w),
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.tp3w(tp3w)
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.tp3w(tp3w)
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);
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);
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//
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//
|
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// Instantiation of DMMU
|
|
//
|
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dmmu dmmu(
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// Rst and clk
|
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.clk(clk),
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.rst(rst),
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// LSU i/f
|
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.dmmu_en(dmmu_en),
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.supv(supv),
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.dmmulsu_vaddr(dclsu_addr),
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.dmmulsu_lsuop(dclsu_lsuop),
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.dmmulsu_stall(),
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// Except I/F
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.dmmuexcept_miss(dmmuexcept_miss),
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.dmmuexcept_fault(dmmuexcept_fault),
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// SPR access
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.spr_cs(spr_cs[`SPR_GROUP_DMMU]),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(spr_dat_dmmu),
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// DC i/f
|
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.dcdmmu_paddr(dcdmmu_paddr)
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);
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|
|
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//
|
// Instantiation of Data Cache
|
// Instantiation of Data Cache
|
//
|
//
|
dc dc(
|
dc dc(
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.clk(clk),
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.clk(clk),
|
.rst(rst),
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.rst(rst),
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.clkdiv_by_2(clkdiv_by_2),
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.clkdiv_by_2(clkdiv_by_2),
|
|
|
// These connect DC to CPU's LSU
|
// These connect DC to CPU's LSU
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.dclsu_addr(dclsu_addr),
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.dclsu_addr(dcdmmu_paddr),
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.dclsu_lsuop(dclsu_lsuop),
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.dclsu_lsuop(dclsu_lsuop),
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.dclsu_datain(dclsu_to_dc),
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.dclsu_datain(dclsu_to_dc),
|
.dclsu_dataout(dclsu_from_dc),
|
.dclsu_dataout(dclsu_from_dc),
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.dclsu_stall(dclsu_stall),
|
.dclsu_stall(dclsu_stall),
|
|
.dclsu_unstall(dclsu_unstall),
|
.dc_en(dc_en),
|
.dc_en(dc_en),
|
|
|
// These connect DC to BIU
|
// These connect DC to BIU
|
.dcbiu_rdy(dcbiu_rdy),
|
.dcbiu_rdy(dcbiu_rdy),
|
.dcbiu_datain(dcbiu_from_biu),
|
.dcbiu_datain(dcbiu_from_biu),
|
