| Line 73... |
Line 73... |
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// Data WISHBONE INTERFACE
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// Data WISHBONE INTERFACE
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dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
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// Trace
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// External Debug Interface
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tp_dir_in, tp_sel, tp_in, tp_out,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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// Power Management
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// Power Management
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pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
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pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
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pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
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pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
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| Line 131... |
Line 132... |
output dwb_we_o; // indicates write transfer
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output dwb_we_o; // indicates write transfer
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output [3:0] dwb_sel_o; // byte select outputs
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output [3:0] dwb_sel_o; // byte select outputs
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output [dw-1:0] dwb_dat_o; // output data bus
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output [dw-1:0] dwb_dat_o; // output data bus
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//
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//
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// External Debug Interface
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//
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input dbg_stall_i; // External Stall Input
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input [dw-1:0] dbg_dat_i; // External Data Input
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input [aw-1:0] dbg_adr_i; // External Address Input
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input [2:0] dbg_op_i; // External Operation Select Input
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input dbg_ewt_i; // External Watchpoint Trigger Input
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output [3:0] dbg_lss_o; // External Load/Store Unit Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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//
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// Power Management
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// Power Management
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//
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//
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input pm_cpustall;
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input pm_cpustall;
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output pm_clksd;
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output pm_clksd;
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output pm_dc_gate;
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output pm_dc_gate;
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| Line 144... |
Line 159... |
output pm_tt_gate;
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output pm_tt_gate;
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output pm_cpu_gate;
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output pm_cpu_gate;
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output pm_wakeup;
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output pm_wakeup;
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output pm_lvolt;
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output pm_lvolt;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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//
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//
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| Line 244... |
Line 260... |
//
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//
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wire [dw-1:0] spr_dat_tt;
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wire [dw-1:0] spr_dat_tt;
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wire tt_int;
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wire tt_int;
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//
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//
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// CPU and external Trace port
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//
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input tp_dir_in;
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input [1:0] tp_sel;
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input [dw-1:0] tp_in;
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output [dw-1:0] tp_out;
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//
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// Trace port and caches/MMUs
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// Trace port and caches/MMUs
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//
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//
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wire [`TP2W_WIDTH-1:0] tp2w;
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wire [`TP2W_WIDTH-1:0] tp2w;
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wire [`TP3W_WIDTH-1:0] tp3w;
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wire [`TP3W_WIDTH-1:0] tp3w;
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| Line 363... |
Line 371... |
.icfetch_op(icfetch_op),
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.icfetch_op(icfetch_op),
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.icfetch_dataout(icfetch_dataout),
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.icfetch_dataout(icfetch_dataout),
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.icfetch_stall(icfetch_stall),
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.icfetch_stall(icfetch_stall),
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.ic_en(ic_en),
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.ic_en(ic_en),
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// SPR access
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.spr_cs(spr_cs[`SPR_GROUP_IC]),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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// These connect IC to BIU
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// These connect IC to BIU
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.icbiu_rdy(icbiu_rdy),
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.icbiu_rdy(icbiu_rdy),
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.icbiu_datain(icbiu_from_biu),
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.icbiu_datain(icbiu_from_biu),
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.icbiu_addr(icbiu_addr),
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.icbiu_addr(icbiu_addr),
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.icbiu_read(icbiu_read),
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.icbiu_read(icbiu_read),
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.icbiu_sel(icbiu_sel),
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.icbiu_sel(icbiu_sel)
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// These connect IC to SPRS
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.spr_dat_i(spr_dat_cpu)
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);
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);
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//
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//
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// Instantiation of Instruction Cache
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// Instantiation of Instruction Cache
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//
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//
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| Line 389... |
Line 400... |
.ic_stall(icfetch_stall),
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.ic_stall(icfetch_stall),
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.ic_fetchop(icfetch_op),
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.ic_fetchop(icfetch_op),
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.ic_en(ic_en),
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.ic_en(ic_en),
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// Connection CPU to external Trace port
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// Connection CPU to external Trace port
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.tp_dir_in(tp_dir_in),
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.tp_dir_in(1'b0),
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.tp_sel(tp_sel),
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.tp_sel(2'b00),
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.tp_in(tp_in),
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.tp_in(32'h00000000),
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.tp_out(tp_out),
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.tp_out(),
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// Connection IMMU and CPU internally
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// Connection IMMU and CPU internally
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.immu_en(immu_en),
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.immu_en(immu_en),
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.immuexcept_miss(immuexcept_miss),
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.immuexcept_miss(immuexcept_miss),
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.immuexcept_fault(immuexcept_fault),
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.immuexcept_fault(immuexcept_fault),
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| Line 480... |
Line 491... |
.dclsu_dataout(dclsu_from_dc),
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.dclsu_dataout(dclsu_from_dc),
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.dclsu_stall(dclsu_stall),
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.dclsu_stall(dclsu_stall),
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.dclsu_unstall(dclsu_unstall),
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.dclsu_unstall(dclsu_unstall),
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.dc_en(dc_en),
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.dc_en(dc_en),
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// SPR access
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.spr_cs(spr_cs[`SPR_GROUP_DC]),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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// These connect DC to BIU
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// These connect DC to BIU
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.dcbiu_rdy(dcbiu_rdy),
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.dcbiu_rdy(dcbiu_rdy),
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.dcbiu_datain(dcbiu_from_biu),
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.dcbiu_datain(dcbiu_from_biu),
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.dcbiu_dataout(dcbiu_to_biu),
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.dcbiu_dataout(dcbiu_to_biu),
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.dcbiu_addr(dcbiu_addr),
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.dcbiu_addr(dcbiu_addr),
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| Line 494... |
Line 511... |
// Trace port
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// Trace port
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.tp2w(tp2w)
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.tp2w(tp2w)
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);
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);
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//
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//
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// Instantiation of Debug Unit
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//
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du du(
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// RISC Internal Interface
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.clk(clk),
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.rst(rst),
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.dclsu_lsuop(dclsu_lsuop),
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.icfetch_op(icfetch_op),
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// DU's access to SPR unit
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.du_stall(),
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.du_addr(),
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.du_dat_i(32'h00000000),
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.du_dat_o(),
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.du_read(),
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.du_write(),
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// Access to DU's SPRs
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.spr_cs(spr_cs[`SPR_GROUP_DU]),
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.spr_write(spr_we),
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.spr_addr(spr_addr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_o(),
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// External Debug Interface
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.dbg_stall_i(dbg_stall_i),
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.dbg_dat_i(dbg_dat_i),
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.dbg_adr_i(dbg_adr_i),
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.dbg_op_i(dbg_op_i),
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.dbg_ewt_i(dbg_ewt_i),
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.dbg_lss_o(dbg_lss_o),
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.dbg_is_o(dbg_is_o),
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.dbg_wp_o(dbg_wp_o),
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.dbg_bp_o(dbg_bp_o),
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.dbg_dat_o(dbg_dat_o)
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);
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//
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// Programmable interrupt controller
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// Programmable interrupt controller
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//
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//
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pic pic(
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pic pic(
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// RISC Internal Interface
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// RISC Internal Interface
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.clk(clk),
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.clk(clk),
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