URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Diff between revs 209 and 210

Rev 209	Rev 210
Line 268...	Line 268...
`wire du_stall;`	`wire du_stall;`
`wire [dw-1:0] du_addr;`	`wire [dw-1:0] du_addr;`
`wire [dw-1:0] du_dat_du;`	`wire [dw-1:0] du_dat_du;`
`wire du_read;`	`wire du_read;`
`wire du_write;`	`wire du_write;`
	wire [`EXCEPT_WIDTH-1:0] du_except;

`//`	`//`
`// Assignments`	`// Assignments`
`//`	`//`
`assign int_high_tt = int_high \| tt_int;`	`assign int_high_tt = int_high \| tt_int;`
Line 409...	Line 410...
`.du_stall(du_stall),`	`.du_stall(du_stall),`
`.du_addr(du_addr),`	`.du_addr(du_addr),`
`.du_dat_du(du_dat_du),`	`.du_dat_du(du_dat_du),`
`.du_read(du_read),`	`.du_read(du_read),`
`.du_write(du_write),`	`.du_write(du_write),`
	`.du_except(du_except),`

`// Connection IMMU and CPU internally`	`// Connection IMMU and CPU internally`
`.immu_en(immu_en),`	`.immu_en(immu_en),`
`.immuexcept_miss(immuexcept_miss),`	`.immuexcept_miss(immuexcept_miss),`
`.immuexcept_fault(immuexcept_fault),`	`.immuexcept_fault(immuexcept_fault),`
Line 526...	Line 528...
`.du_addr(du_addr),`	`.du_addr(du_addr),`
`.du_dat_i(spr_dat_cpu),`	`.du_dat_i(spr_dat_cpu),`
`.du_dat_o(du_dat_du),`	`.du_dat_o(du_dat_du),`
`.du_read(du_read),`	`.du_read(du_read),`
`.du_write(du_write),`	`.du_write(du_write),`
	`.du_except(du_except),`

`// Access to DU's SPRs`	`// Access to DU's SPRs`
.spr_cs(spr_cs[`SPR_GROUP_DU]),	.spr_cs(spr_cs[`SPR_GROUP_DU]),
`.spr_write(spr_we),`	`.spr_write(spr_we),`
`.spr_addr(spr_addr),`	`.spr_addr(spr_addr),`