URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 210	Rev 215
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
	`// no message`
	`//`
`// Revision 1.4 2001/08/13 03:36:20 lampret`	`// Revision 1.4 2001/08/13 03:36:20 lampret`
`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`	`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
`//`	`//`
`// Revision 1.3 2001/08/09 13:39:33 lampret`	`// Revision 1.3 2001/08/09 13:39:33 lampret`
`// Major clean-up.`	`// Major clean-up.`
Line 270...	Line 273...
`wire [dw-1:0] du_dat_du;`	`wire [dw-1:0] du_dat_du;`
`wire du_read;`	`wire du_read;`
`wire du_write;`	`wire du_write;`
wire [`EXCEPT_WIDTH-1:0] du_except;	wire [`EXCEPT_WIDTH-1:0] du_except;

	`wire ex_freeze;`
	wire [`BRANCHOP_WIDTH-1:0] branch_op;

`//`	`//`
`// Assignments`	`// Assignments`
`//`	`//`
`assign int_high_tt = int_high \| tt_int;`	`assign int_high_tt = int_high \| tt_int;`

Line 405...	Line 411...
`.ic_stall(icfetch_stall),`	`.ic_stall(icfetch_stall),`
`.ic_fetchop(icfetch_op),`	`.ic_fetchop(icfetch_op),`
`.ic_en(ic_en),`	`.ic_en(ic_en),`

`// Connection CPU to external Trace port`	`// Connection CPU to external Trace port`
	`.ex_freeze(ex_freeze),`
	`.branch_op(branch_op),`
`.du_stall(du_stall),`	`.du_stall(du_stall),`
`.du_addr(du_addr),`	`.du_addr(du_addr),`
`.du_dat_du(du_dat_du),`	`.du_dat_du(du_dat_du),`
`.du_read(du_read),`	`.du_read(du_read),`
`.du_write(du_write),`	`.du_write(du_write),`
Line 444...	Line 452...
`.spr_dat_pic(spr_dat_pic),`	`.spr_dat_pic(spr_dat_pic),`
`.spr_dat_tt(spr_dat_tt),`	`.spr_dat_tt(spr_dat_tt),`
`.spr_dat_pm(spr_dat_pm),`	`.spr_dat_pm(spr_dat_pm),`
`.spr_dat_dmmu(spr_dat_dmmu),`	`.spr_dat_dmmu(spr_dat_dmmu),`
`.spr_dat_immu(spr_dat_immu),`	`.spr_dat_immu(spr_dat_immu),`
	`.spr_dat_du(spr_dat_du),`
`.spr_cs(spr_cs),`	`.spr_cs(spr_cs),`
`.spr_we(spr_we)`	`.spr_we(spr_we)`
`);`	`);`

`//`	`//`
Line 520...	Line 529...
`// RISC Internal Interface`	`// RISC Internal Interface`
`.clk(clk),`	`.clk(clk),`
`.rst(rst),`	`.rst(rst),`
`.dclsu_lsuop(dclsu_lsuop),`	`.dclsu_lsuop(dclsu_lsuop),`
`.icfetch_op(icfetch_op),`	`.icfetch_op(icfetch_op),`
	`.ex_freeze(ex_freeze),`
	`.branch_op(branch_op),`

`// DU's access to SPR unit`	`// DU's access to SPR unit`
`.du_stall(du_stall),`	`.du_stall(du_stall),`
`.du_addr(du_addr),`	`.du_addr(du_addr),`
`.du_dat_i(spr_dat_cpu),`	`.du_dat_i(spr_dat_cpu),`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Diff between revs 210 and 215