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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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`include "defines.v"
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`include "defines.v"
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module reg2mem(addr, lsu_op, regdata, memdata);
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module reg2mem(addr, lsu_op, regdata, memdata);
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parameter width = `OPERAND_WIDTH;
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parameter width = `OPERAND_WIDTH;
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//
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//
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// Mux to memdata[31:24]
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// Mux to memdata[31:24]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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{`LSUOP_SB, 2'b00} : memdata[31:24] <= #1 regdata[7:0];
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{`LSUOP_SB, 2'b00} : memdata[31:24] = regdata[7:0];
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{`LSUOP_SH, 2'b00} : memdata[31:24] <= #1 regdata[15:8];
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{`LSUOP_SH, 2'b00} : memdata[31:24] = regdata[15:8];
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default : memdata[31:24] <= #1 regdata[31:24];
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default : memdata[31:24] = regdata[31:24];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[23:16]
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// Mux to memdata[23:16]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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{`LSUOP_SW, 2'b00} : memdata[23:16] <= #1 regdata[23:16];
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{`LSUOP_SW, 2'b00} : memdata[23:16] = regdata[23:16];
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default : memdata[23:16] <= #1 regdata[7:0];
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default : memdata[23:16] = regdata[7:0];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[15:8]
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// Mux to memdata[15:8]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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{`LSUOP_SB, 2'b10} : memdata[15:8] <= #1 regdata[7:0];
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{`LSUOP_SB, 2'b10} : memdata[15:8] = regdata[7:0];
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default : memdata[15:8] <= #1 regdata[15:8];
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default : memdata[15:8] = regdata[15:8];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[7:0]
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// Mux to memdata[7:0]
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//
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//
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always @(regdata)
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always @(regdata)
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memdata[7:0] <= #1 regdata[7:0];
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memdata[7:0] = regdata[7:0];
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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