| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2001/10/14 13:12:10 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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// no message
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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// Major clean-up.
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| Line 73... |
Line 76... |
output [width-1:0] memdata;
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output [width-1:0] memdata;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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reg [width-1:0] memdata;
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reg [7:0] memdata_hh;
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reg [7:0] memdata_hl;
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reg [7:0] memdata_lh;
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reg [7:0] memdata_ll;
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assign memdata = {memdata_hh, memdata_hl, memdata_lh, memdata_ll};
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//
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//
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// Mux to memdata[31:24]
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// Mux to memdata[31:24]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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{`LSUOP_SB, 2'b00} : memdata[31:24] = regdata[7:0];
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{`LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
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{`LSUOP_SH, 2'b00} : memdata[31:24] = regdata[15:8];
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{`LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
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default : memdata[31:24] = regdata[31:24];
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default : memdata_hh = regdata[31:24];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[23:16]
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// Mux to memdata[23:16]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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{`LSUOP_SW, 2'b00} : memdata[23:16] = regdata[23:16];
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{`LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
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default : memdata[23:16] = regdata[7:0];
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default : memdata_hl = regdata[7:0];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[15:8]
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// Mux to memdata[15:8]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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{`LSUOP_SB, 2'b10} : memdata[15:8] = regdata[7:0];
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{`LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
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default : memdata[15:8] = regdata[15:8];
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default : memdata_lh = regdata[15:8];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[7:0]
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// Mux to memdata[7:0]
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//
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//
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always @(regdata)
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always @(regdata)
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memdata[7:0] = regdata[7:0];
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memdata_ll = regdata[7:0];
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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