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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/07/22 03:31:54 lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Revision 1.1 2001/07/20 00:46:21 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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`include "general.h"
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`include "timescale.v"
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`include "defines.v"
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module rf(
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// Clock and reset
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clk, rst,
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//`define XCV_RF
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// Write i/f
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`define ART_DP
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addrw, dataw, we,
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module rf(clk, rst, addrw, dataw, pipeline_freeze, we, addra, dataa, addrb, datab,
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// Read i/f
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rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w, tpdw
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pipeline_freeze, addra, addrb, dataa, datab,
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// Debug
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rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w
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);
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);
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parameter dw = `OPERAND_WIDTH;
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parameter dw = `OPERAND_WIDTH;
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parameter aw = `REGFILE_ADDR_WIDTH;
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parameter aw = `REGFILE_ADDR_WIDTH;
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input clk, rst, pipeline_freeze, we;
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//
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// I/O
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//
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input [dw-1:0] dataw;
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//
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output [dw-1:0] dataa;
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// Clock and reset
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output [dw-1:0] datab;
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//
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input clk;
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input rst;
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//
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// Write i/f
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//
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input [aw-1:0] addrw;
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input [aw-1:0] addrw;
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input [dw-1:0] dataw;
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input we;
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//
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// Read i/f
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//
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input pipeline_freeze;
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input [aw-1:0] addra;
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input [aw-1:0] addra;
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input [aw-1:0] addrb;
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input [aw-1:0] addrb;
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output [dw-1:0] dataa;
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output [dw-1:0] datab;
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// Trace port
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//
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// Debug
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//
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output [31:0] rfa_tqa;
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output [31:0] rfa_tqa;
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output [31:0] rfb_tqa;
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output [31:0] rfb_tqa;
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output [`TP1R_WIDTH-1:0] rfa_tmuxed;
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output [`TP1R_WIDTH-1:0] rfa_tmuxed;
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output [`TP1R_WIDTH-1:0] rfb_tmuxed;
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output [`TP1R_WIDTH-1:0] rfb_tmuxed;
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input [`TP1W_WIDTH-1:0] tp1w;
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input [`TP1W_WIDTH-1:0] tp1w;
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input [31:0] tpdw;
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wire [dw-1:0] from_rfa, from_rfb;
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//
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// Internal wires and regs
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//
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wire [dw-1:0] from_rfa;
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wire [dw-1:0] from_rfb;
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wire [dw-1:0] t_dataw; // for test port
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wire [dw-1:0] t_dataw; // for test port
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wire [aw-1:0] t_addrw; // for test port
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wire [aw-1:0] t_addrw; // for test port
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wire [aw-1:0] t_addra; // for test port
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wire [aw-1:0] t_addra; // for test port
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wire [aw-1:0] t_addrb; // for test port
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wire [aw-1:0] t_addrb; // for test port
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reg [dw:0] dataa_saved;
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reg [dw:0] datab_saved;
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reg [dw:0] dataa_saved, datab_saved;
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//
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// Simple assignments
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//
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assign rfa_tqa = 32'b0;
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assign rfb_tqa = 32'b0;
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assign rfa_tmuxed = `TP1R_WIDTH'b0;
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assign rfb_tmuxed = `TP1R_WIDTH'b0;
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//
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// Operand A comes from RF or from saved A register
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//
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assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
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assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
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//
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// Operand B comes from RF or from saved B register
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//
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assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
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assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
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//
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// Stores operand from RF_A into temp reg when pipeline is frozen
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// Stores operand from RF_A into temp reg when pipeline is frozen
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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dataa_saved <= #1 33'b0;
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dataa_saved <= #1 33'b0;
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end
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end
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else if (pipeline_freeze & !dataa_saved[32]) begin
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else if (pipeline_freeze & !dataa_saved[32]) begin
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dataa_saved <= #1 {1'b1, from_rfa};
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dataa_saved <= #1 {1'b1, from_rfa};
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end
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end
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else if (!pipeline_freeze)
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else if (!pipeline_freeze)
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dataa_saved[32] <= #1 1'b0;
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dataa_saved[32] <= #1 1'b0;
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//
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// Stores operand from RF_B into temp reg when pipeline is frozen
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// Stores operand from RF_B into temp reg when pipeline is frozen
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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datab_saved <= #1 33'b0;
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datab_saved <= #1 33'b0;
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end
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end
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else if (pipeline_freeze & !datab_saved[32]) begin
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else if (pipeline_freeze & !datab_saved[32]) begin
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datab_saved <= #1 {1'b1, from_rfb};
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datab_saved <= #1 {1'b1, from_rfb};
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end
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end
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else if (!pipeline_freeze)
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else if (!pipeline_freeze)
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datab_saved[32] <= #1 1'b0;
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datab_saved[32] <= #1 1'b0;
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`ifdef XCV_RF
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//
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// Instantiation of register file memory (A)
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// Instantiation of register file dual-port RAM A
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xcv_rfram rf(
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//
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.clk(clk),
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generic_dpram_32x32 rf_a(
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.rst(rst),
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// Port A
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.we(we),
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.clk_a(clk),
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.addrw(addrw),
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.rst_a(rst),
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.dataw(dataw),
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.ce_a(1'b1),
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.addra(addra),
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.oe_a(1'b1),
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.dataa(from_rfa),
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.addr_a(addra),
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.addrb(addrb),
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.do_a(from_rfa),
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.datab(from_rfb)
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);
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// Port B
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.clk_b(clk),
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`else
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.rst_b(rst),
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.ce_b(we),
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`ifdef ART_DP
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.we_b(we),
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// Instatiation of dual port high density artisan sram memory
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.addr_b(addrw),
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art_hsdp_32x32 rf_a(
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.di_b(dataw)
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.qa(from_rfa),
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.clka(clk),
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.cena(1'b0),
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.wena(1'b1),
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.aa(addra),
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.da(32'b0),
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.oena(1'b0),
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.qb(),
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.clkb(clk),
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.cenb(~we),
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.wenb(1'b0),
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.ab(addrw),
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.db(dataw),
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.oenb(1'b1)
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);
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art_hsdp_32x32 rf_b(
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.qa(from_rfb),
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.clka(clk),
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.cena(1'b0),
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.wena(1'b1),
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.aa(addrb),
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.da(32'b0),
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.oena(1'b0),
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.qb(),
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.clkb(clk),
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.cenb(~we),
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.wenb(1'b0),
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.ab(addrw),
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.db(dataw),
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.oenb(1'b1)
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);
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assign rfa_tqa = 32'b0;
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assign rfb_tqa = 32'b0;
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assign rfa_tmuxed = `TP1R_WIDTH'b0;
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assign rfb_tmuxed = `TP1R_WIDTH'b0;
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`else
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// Instantiation of register file memory (A)
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art_rf2r_32x32 rf_a(
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.QA(from_rfa),
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.OENSQA(rfa_tmuxed[`TP1R_RF_OENSQA]),
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.ASQA(rfa_tmuxed[`TP1R_RF_ASQA]),
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.TQA(rfa_tqa),
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.QSQA(rfa_tmuxed[`TP1R_RF_QSQA]),
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.DSOB(rfa_tmuxed[`TP1R_RF_DSOB]),
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.CENSQB(rfa_tmuxed[`TP1R_RF_CENSQB]),
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.ASQB(rfa_tmuxed[`TP1R_RF_ASQB]),
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.CLKA(clk),
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.CENA(1'b0),
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.OENA(1'b0),
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.AA(addra),
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.TISA(tp1w[`TP1W_RF_TISA]),
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.TMSA(tp1w[`TP1W_RF_TMSA]),
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.TCENA(tp1w[`TP1W_RF_TCENA]),
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.TOENA(tp1w[`TP1W_RF_TOENA]),
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.TQOENA(tp1w[`TP1W_RF_TQOENA]),
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.TAA(tp1w[`TP1W_RF_TAA]),
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.CLKB(clk),
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.CENB(~we),
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.AB(addrw),
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.DB(dataw),
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.TISB(tp1w[`TP1W_RF_TISB]),
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.TMSB(tp1w[`TP1W_RF_TMSB]),
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.TCENB(tp1w[`TP1W_RF_TCENB]),
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.TAB(tp1w[`TP1W_RF_TAB]),
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.TDB(tpdw),
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.SMSB(tp1w[`TP1W_RF_SMSB]),
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.DSIB(tp1w[`TP1W_RF_DSIB])
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);
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);
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// Instantiation of register file memory (B)
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//
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art_rf2r_32x32 rf_b(
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// Instantiation of register file dual-port RAM B
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.QA(from_rfb),
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//
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generic_dpram_32x32 rf_b(
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.OENSQA(rfb_tmuxed[`TP1R_RF_OENSQA]),
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// Port A
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.ASQA(rfb_tmuxed[`TP1R_RF_ASQA]),
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.clk_a(clk),
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.TQA(rfb_tqa),
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.rst_a(rst),
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.QSQA(rfb_tmuxed[`TP1R_RF_QSQA]),
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.ce_a(1'b1),
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.DSOB(rfb_tmuxed[`TP1R_RF_DSOB]),
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.oe_a(1'b1),
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.CENSQB(rfb_tmuxed[`TP1R_RF_CENSQB]),
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.addr_a(addrb),
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.ASQB(rfb_tmuxed[`TP1R_RF_ASQB]),
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.do_a(from_rfb),
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.CLKA(clk),
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// Port B
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.CENA(1'b0),
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.clk_b(clk),
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.OENA(1'b0),
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.rst_b(rst),
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.AA(addrb),
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.ce_b(we),
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.TISA(tp1w[`TP1W_RF_TISA]),
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.we_b(we),
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.TMSA(tp1w[`TP1W_RF_TMSA]),
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.addr_b(addrw),
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.TCENA(tp1w[`TP1W_RF_TCENA]),
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.di_b(dataw)
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.TOENA(tp1w[`TP1W_RF_TOENA]),
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.TQOENA(tp1w[`TP1W_RF_TQOENA]),
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.TAA(tp1w[`TP1W_RF_TAA]),
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.CLKB(clk),
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.CENB(~we),
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.AB(addrw),
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.DB(dataw),
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.TISB(tp1w[`TP1W_RF_TISB]),
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.TMSB(tp1w[`TP1W_RF_TMSB]),
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.TCENB(tp1w[`TP1W_RF_TCENB]),
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.TAB(tp1w[`TP1W_RF_TAB]),
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.TDB(tpdw),
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.SMSB(tp1w[`TP1W_RF_SMSB]),
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.DSIB(tp1w[`TP1W_RF_DSIB])
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);
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);
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`endif
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`endif
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/*
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art_rf2r_32x32 rf_a(
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.qa(from_rfa),
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.oensqa(rfa_tmuxed[`TP1R_RF_OENSQA]),
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.asqa(rfa_tmuxed[`TP1R_RF_ASQA]),
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.tqa(rfa_tqa),
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.qsqa(rfa_tmuxed[`TP1R_RF_QSQA]),
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.dsob(rfa_tmuxed[`TP1R_RF_DSOB]),
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.censqb(rfa_tmuxed[`TP1R_RF_CENSQB]),
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.asqb(rfa_tmuxed[`TP1R_RF_ASQB]),
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.clka(clk),
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.cena(1'b0),
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.oena(1'b0),
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.aa(addra),
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.tisa(tp1w[`TP1W_RF_TISA]),
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.tmsa(tp1w[`TP1W_RF_TMSA]),
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.tcena(tp1w[`TP1W_RF_TCENA]),
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.toena(tp1w[`TP1W_RF_TOENA]),
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.tqoena(tp1w[`TP1W_RF_TQOENA]),
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.taa(tp1w[`TP1W_RF_TAA]),
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.clkb(clk),
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.cenb(~we),
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.ab(addrw),
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.db(dataw),
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.tisb(tp1w[`TP1W_RF_TISB]),
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.tmsb(tp1w[`TP1W_RF_TMSB]),
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.tcenb(tp1w[`TP1W_RF_TCENB]),
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.tab(tp1w[`TP1W_RF_TAB]),
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.tdb(tpdw),
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.smsb(tp1w[`TP1W_RF_SMSB]),
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.dsib(tp1w[`TP1W_RF_DSIB])
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);
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// Instantiation of register file memory (B)
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art_rf2r_32x32 rf_b(
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.qa(from_rfb),
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.oensqa(rfb_tmuxed[`TP1R_RF_OENSQA]),
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.asqa(rfb_tmuxed[`TP1R_RF_ASQA]),
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.tqa(rfb_tqa),
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.qsqa(rfb_tmuxed[`TP1R_RF_QSQA]),
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.dsob(rfb_tmuxed[`TP1R_RF_DSOB]),
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.censqb(rfb_tmuxed[`TP1R_RF_CENSQB]),
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.asqb(rfb_tmuxed[`TP1R_RF_ASQB]),
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.clka(clk),
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.cena(1'b0),
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.oena(1'b0),
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.aa(addrb),
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.tisa(tp1w[`TP1W_RF_TISA]),
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.tmsa(tp1w[`TP1W_RF_TMSA]),
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.tcena(tp1w[`TP1W_RF_TCENA]),
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.toena(tp1w[`TP1W_RF_TOENA]),
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.tqoena(tp1w[`TP1W_RF_TQOENA]),
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.taa(tp1w[`TP1W_RF_TAA]),
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.clkb(clk),
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.cenb(~we),
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.ab(addrw),
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.db(dataw),
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.tisb(tp1w[`TP1W_RF_TISB]),
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.tmsb(tp1w[`TP1W_RF_TMSB]),
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.tcenb(tp1w[`TP1W_RF_TCENB]),
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.tab(tp1w[`TP1W_RF_TAB]),
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.tdb(tpdw),
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.smsb(tp1w[`TP1W_RF_SMSB]),
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.dsib(tp1w[`TP1W_RF_DSIB])
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);
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*/
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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