| Line 66... |
Line 66... |
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// Write i/f
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// Write i/f
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addrw, dataw, we,
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addrw, dataw, we,
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// Read i/f
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// Read i/f
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pipeline_freeze, addra, addrb, dataa, datab,
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id_freeze, addra, addrb, dataa, datab,
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// Debug
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// Debug
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rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w
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rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w
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);
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);
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| Line 95... |
Line 95... |
input we;
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input we;
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//
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//
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// Read i/f
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// Read i/f
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//
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//
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input pipeline_freeze;
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input id_freeze;
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input [aw-1:0] addra;
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input [aw-1:0] addra;
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input [aw-1:0] addrb;
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input [aw-1:0] addrb;
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output [dw-1:0] dataa;
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output [dw-1:0] dataa;
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output [dw-1:0] datab;
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output [dw-1:0] datab;
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| Line 147... |
Line 147... |
//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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dataa_saved <= #1 33'b0;
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dataa_saved <= #1 33'b0;
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end
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end
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else if (pipeline_freeze & !dataa_saved[32]) begin
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else if (id_freeze & !dataa_saved[32]) begin
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dataa_saved <= #1 {1'b1, from_rfa};
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dataa_saved <= #1 {1'b1, from_rfa};
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end
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end
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else if (!pipeline_freeze)
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else if (!id_freeze)
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dataa_saved[32] <= #1 1'b0;
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dataa_saved <= #1 33'b0;
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//
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//
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// Stores operand from RF_B into temp reg when pipeline is frozen
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// Stores operand from RF_B into temp reg when pipeline is frozen
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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datab_saved <= #1 33'b0;
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datab_saved <= #1 33'b0;
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end
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end
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else if (pipeline_freeze & !datab_saved[32]) begin
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else if (id_freeze & !datab_saved[32]) begin
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datab_saved <= #1 {1'b1, from_rfb};
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datab_saved <= #1 {1'b1, from_rfb};
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end
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end
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else if (!pipeline_freeze)
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else if (!id_freeze)
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datab_saved[32] <= #1 1'b0;
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datab_saved <= #1 33'b0;
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//
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//
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// Instantiation of register file two-port RAM A
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// Instantiation of register file two-port RAM A
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//
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//
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generic_tpram_32x32 rf_a(
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generic_tpram_32x32 rf_a(
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