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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [rf.v] - Diff between revs 205 and 209

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Rev 205 Rev 209
Line 69... Line 69... 
 
 
 
 
        // Read i/f
 
        // Read i/f
 
        id_freeze, addra, addrb, dataa, datab,
 
        id_freeze, addra, addrb, dataa, datab,
 
 
 
 
 
        // Debug
 
        // Debug
 
        rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w
 
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
 
);
 
);
 
 
 
 
 
parameter dw = `OPERAND_WIDTH;
 
parameter dw = `OPERAND_WIDTH;
 
parameter aw = `REGFILE_ADDR_WIDTH;
 
parameter aw = `REGFILE_ADDR_WIDTH;
 
 
 
 
Line 102... Line 102... 
input   [aw-1:0]         addrb;
 
input   [aw-1:0]         addrb;
 
output  [dw-1:0]         dataa;
 
output  [dw-1:0]         dataa;
 
output  [dw-1:0]         datab;
 
output  [dw-1:0]         datab;
 
 
 
 
 
//
 
//
 
// Debug
 
// SPR access for debugging purposes
 
//
 
//
 
output  [31:0]                   rfa_tqa;
 
input                           spr_cs;
 
output  [31:0]                   rfb_tqa;
 
input                           spr_write;
 
output  [`TP1R_WIDTH-1:0]        rfa_tmuxed;
 
input   [31:0]                   spr_addr;
 
output  [`TP1R_WIDTH-1:0]        rfb_tmuxed;
 
input   [31:0]                   spr_dat_i;
 
input   [`TP1W_WIDTH-1:0]        tp1w;
 
output  [31:0]                   spr_dat_o;
 
 
 
 
 
//
 
//
 
// Internal wires and regs
 
// Internal wires and regs
 
//
 
//
 
wire    [dw-1:0]         from_rfa;
 
wire    [dw-1:0]         from_rfa;
 
wire    [dw-1:0]         from_rfb;
 
wire    [dw-1:0]         from_rfb;
 
wire    [dw-1:0]         t_dataw; // for test port
 
 
 
wire    [aw-1:0]         t_addrw; // for test port
 
 
 
wire    [aw-1:0]         t_addra; // for test port
 
 
 
wire    [aw-1:0]         t_addrb; // for test port
 
 
 
reg     [dw:0]                   dataa_saved;
 
reg     [dw:0]                   dataa_saved;
 
reg     [dw:0]                   datab_saved;
 
reg     [dw:0]                   datab_saved;
 
 
 
wire    [aw-1:0]         rf_addra;
 
 
 
wire    [aw-1:0]         rf_addrw;
 
 
 
wire    [dw-1:0]         rf_dataw;
 
 
 
wire                            rf_we;
 
 
 
wire                            spr_valid;
 
 
 
 
 
 
 
//
 
 
 
// SPR access is valid when spr_cs is asserted and
 
 
 
// SPR address matches GPR addresses
 
 
 
//
 
 
 
assign spr_valid = spr_cs & (spr_addr[10:5] == `SPR_RF);
 
 
 
 
 
//
 
//
 
// Simple assignments
 
// SPR data output is always from RF A
 
//
 
//
 
assign rfa_tqa = 32'b0;
 
assign spr_dat_o = from_rfa;
 
assign rfb_tqa = 32'b0;
 
 
 
assign rfa_tmuxed = `TP1R_WIDTH'b0;
 
 
 
assign rfb_tmuxed = `TP1R_WIDTH'b0;
 
 
 
 
 
 
 
//
 
//
 
// Operand A comes from RF or from saved A register
 
// Operand A comes from RF or from saved A register
 
//
 
//
 
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
 
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
Line 141... Line 145... 
// Operand B comes from RF or from saved B register
 
// Operand B comes from RF or from saved B register
 
//
 
//
 
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
 
 
 
 
//
 
//
 
 
 
// RF A read address is either from SPRS or normal from CPU control
 
 
 
//
 
 
 
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
 
 
 
 
 
 
 
//
 
 
 
// RF write address is either from SPRS or normal from CPU control
 
 
 
//
 
 
 
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
 
 
 
 
 
 
 
//
 
 
 
// RF write data is either from SPRS or normal from CPU datapath
 
 
 
//
 
 
 
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
 
 
 
 
 
 
 
//
 
 
 
// RF write enable is either from SPRS or normal from CPU control
 
 
 
//
 
 
 
assign rf_we = (spr_valid & spr_write) | we;
 
 
 
 
 
 
 
//
 
// Stores operand from RF_A into temp reg when pipeline is frozen
 
// Stores operand from RF_A into temp reg when pipeline is frozen
 
//
 
//
 
always @(posedge clk or posedge rst)
 
always @(posedge clk or posedge rst)
 
        if (rst) begin
 
        if (rst) begin
 
                dataa_saved <= #1 33'b0;
 
                dataa_saved <= #1 33'b0;
Line 176... Line 200... 
        .clk_a(clk),
 
        .clk_a(clk),
 
        .rst_a(rst),
 
        .rst_a(rst),
 
        .ce_a(1'b1),
 
        .ce_a(1'b1),
 
        .we_a(1'b0),
 
        .we_a(1'b0),
 
        .oe_a(1'b1),
 
        .oe_a(1'b1),
 
        .addr_a(addra),
 
        .addr_a(rf_addra),
 
        .di_a(32'h0000_0000),
 
        .di_a(32'h0000_0000),
 
        .do_a(from_rfa),
 
        .do_a(from_rfa),
 
 
 
 
 
        // Port B
 
        // Port B
 
        .clk_b(clk),
 
        .clk_b(clk),
 
        .rst_b(rst),
 
        .rst_b(rst),
 
        .ce_b(we),
 
        .ce_b(rf_we),
 
        .we_b(we),
 
        .we_b(rf_we),
 
        .oe_b(1'b0),
 
        .oe_b(1'b0),
 
        .addr_b(addrw),
 
        .addr_b(rf_addrw),
 
        .di_b(dataw),
 
        .di_b(rf_dataw),
 
        .do_b()
 
        .do_b()
 
);
 
);
 
 
 
 
 
//
 
//
 
// Instantiation of register file two-port RAM B
 
// Instantiation of register file two-port RAM B
Line 208... Line 232... 
        .do_a(from_rfb),
 
        .do_a(from_rfb),
 
 
 
 
 
        // Port B
 
        // Port B
 
        .clk_b(clk),
 
        .clk_b(clk),
 
        .rst_b(rst),
 
        .rst_b(rst),
 
        .ce_b(we),
 
        .ce_b(rf_we),
 
        .we_b(we),
 
        .we_b(rf_we),
 
        .oe_b(1'b0),
 
        .oe_b(1'b0),
 
        .addr_b(addrw),
 
        .addr_b(rf_addrw),
 
        .di_b(dataw),
 
        .di_b(rf_dataw),
 
        .do_b()
 
        .do_b()
 
);
 
);
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
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