| Line 64... |
Line 64... |
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// Internal CPU interface
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// Internal CPU interface
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flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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epcr, eear, esr, except_start, except_started,
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epcr, eear, esr, except_start, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, sr,
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to_wbmux, epcr_we, eear_we, esr_we, sr,
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spr_dat_cfgr, spr_dat_dmmu,
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spr_dat_cfgr, spr_dat_rf,
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_addr, spr_dataout, spr_cs, spr_we
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_addr, spr_dataout, spr_cs, spr_we,
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du_addr, du_dat_du, du_read,
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du_write
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);
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);
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parameter width = `OPERAND_WIDTH;
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parameter width = `OPERAND_WIDTH;
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//
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//
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| Line 99... |
Line 104... |
output epcr_we; // EPCR0 write enable
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output epcr_we; // EPCR0 write enable
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output eear_we; // EEAR0 write enable
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output eear_we; // EEAR0 write enable
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output esr_we; // ESR0 write enable
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output esr_we; // ESR0 write enable
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output [`SR_WIDTH-1:0] sr; // SR
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output [`SR_WIDTH-1:0] sr; // SR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_cfgr; // Data from CFGR
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input [31:0] spr_dat_rf; // Data from RF
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//
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//
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// To/from other RISC units
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// To/from other RISC units
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//
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//
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_pic; // Data from PIC
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input [31:0] spr_dat_tt; // Data from TT
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input [31:0] spr_dat_tt; // Data from TT
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input [31:0] spr_dat_pm; // Data from PM
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input [31:0] spr_dat_pm; // Data from PM
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input [31:0] spr_dat_dmmu; // Data from DMMU
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input [31:0] spr_dat_dmmu; // Data from DMMU
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input [31:0] spr_dat_immu; // Data from IMMU
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input [31:0] spr_dat_du; // Data from DU
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output [31:0] spr_addr; // SPR Address
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output [31:0] spr_addr; // SPR Address
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output [31:0] spr_dataout; // Data to unit
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output [31:0] spr_dataout; // Data to unit
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output [31:0] spr_cs; // Unit select
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output [31:0] spr_cs; // Unit select
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output spr_we; // SPR write enable
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output spr_we; // SPR write enable
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//
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//
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// To/from Debug Unit
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//
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input [width-1:0] du_addr; // Address
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input [width-1:0] du_dat_du; // Data from DU to SPRS
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input du_read; // Read qualifier
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input du_write; // Write qualifier
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//
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// Internal regs & wires
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// Internal regs & wires
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//
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//
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reg [`SR_WIDTH-1:0] sr; // SR
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reg [`SR_WIDTH-1:0] sr; // SR
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reg write_spr; // Write SPR
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reg write_spr; // Write SPR
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reg read_spr; // Read SPR
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reg read_spr; // Read SPR
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reg [width-1:0] to_wbmux; // For l.mfspr
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reg [width-1:0] to_wbmux; // For l.mfspr
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reg [31:0] spr_cs; // Group selects
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wire sr_we; // Write enable SR
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wire sr_we; // Write enable SR
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wire cfgr_sel; // Select for cfg regs
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wire cfgr_sel; // Select for cfg regs
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wire rf_sel; // Select for RF
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wire sr_sel; // Select for SR
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wire sr_sel; // Select for SR
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wire epcr_sel; // Select for EPCR0
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wire epcr_sel; // Select for EPCR0
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wire eear_sel; // Select for EEAR0
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wire eear_sel; // Select for EEAR0
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wire esr_sel; // Select for ESR0
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wire esr_sel; // Select for ESR0
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wire [31:0] sys_data; // Read data from system SPRs
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wire [31:0] sys_data; // Read data from system SPRs
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wire [`SR_WIDTH-1:0] to_sr; // Data to SR
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wire [`SR_WIDTH-1:0] to_sr; // Data to SR
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wire du_access; // Debug unit access
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wire [`ALUOP_WIDTH-1:0] sprs_op; // ALU operation
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reg [31:0] unqualified_cs; // Unqualified chip selects
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//
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// Decide if it is debug unit access
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//
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assign du_access = du_read | du_write;
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//
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// Generate sprs opcode
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//
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assign sprs_op = du_write ? `ALUOP_MTSR : du_read ? `ALUOP_MFSR : alu_op;
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//
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//
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// Generate SPR address from base address and offset
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// Generate SPR address from base address and offset
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// OR from debug unit address
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//
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//
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assign spr_addr = addrbase + addrofs;
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assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};
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//
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//
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// SPR is written with dat_i
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// SPR is written with dat_i from l.mtspr
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// OR by debug unit
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//
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//
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assign spr_dataout = dat_i;
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assign spr_dataout = du_access ? du_dat_du : dat_i;
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//
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//
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// Write into SPRs when l.mtspr
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// Write into SPRs when l.mtspr
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//
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//
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assign spr_we = write_spr;
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assign spr_we = du_write | write_spr;
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//
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// Qualify chip selects
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//
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assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
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//
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//
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// Decoding of groups
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// Decoding of groups
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//
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//
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always @(spr_addr)
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always @(spr_addr)
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case (spr_addr[`SPR_GROUP_BITS]) // synopsys parallel_case
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case (spr_addr[`SPR_GROUP_BITS]) // synopsys parallel_case
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`SPR_GROUP_WIDTH'd00: spr_cs = 32'b00000000_00000000_00000000_00000001;
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`SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
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`SPR_GROUP_WIDTH'd01: spr_cs = 32'b00000000_00000000_00000000_00000010;
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`SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
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`SPR_GROUP_WIDTH'd02: spr_cs = 32'b00000000_00000000_00000000_00000100;
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`SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
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`SPR_GROUP_WIDTH'd03: spr_cs = 32'b00000000_00000000_00000000_00001000;
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`SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
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`SPR_GROUP_WIDTH'd04: spr_cs = 32'b00000000_00000000_00000000_00010000;
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`SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
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`SPR_GROUP_WIDTH'd05: spr_cs = 32'b00000000_00000000_00000000_00100000;
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`SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
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`SPR_GROUP_WIDTH'd06: spr_cs = 32'b00000000_00000000_00000000_01000000;
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`SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
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`SPR_GROUP_WIDTH'd07: spr_cs = 32'b00000000_00000000_00000000_10000000;
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`SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
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`SPR_GROUP_WIDTH'd08: spr_cs = 32'b00000000_00000000_00000001_00000000;
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`SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
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`SPR_GROUP_WIDTH'd09: spr_cs = 32'b00000000_00000000_00000010_00000000;
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`SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
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`SPR_GROUP_WIDTH'd10: spr_cs = 32'b00000000_00000000_00000100_00000000;
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`SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
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`SPR_GROUP_WIDTH'd11: spr_cs = 32'b00000000_00000000_00001000_00000000;
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`SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
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`SPR_GROUP_WIDTH'd12: spr_cs = 32'b00000000_00000000_00010000_00000000;
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`SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
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`SPR_GROUP_WIDTH'd13: spr_cs = 32'b00000000_00000000_00100000_00000000;
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`SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
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`SPR_GROUP_WIDTH'd14: spr_cs = 32'b00000000_00000000_01000000_00000000;
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`SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
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`SPR_GROUP_WIDTH'd15: spr_cs = 32'b00000000_00000000_10000000_00000000;
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`SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
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`SPR_GROUP_WIDTH'd16: spr_cs = 32'b00000000_00000001_00000000_00000000;
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`SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
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`SPR_GROUP_WIDTH'd17: spr_cs = 32'b00000000_00000010_00000000_00000000;
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`SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
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`SPR_GROUP_WIDTH'd18: spr_cs = 32'b00000000_00000100_00000000_00000000;
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`SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
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`SPR_GROUP_WIDTH'd19: spr_cs = 32'b00000000_00001000_00000000_00000000;
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`SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
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`SPR_GROUP_WIDTH'd20: spr_cs = 32'b00000000_00010000_00000000_00000000;
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`SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
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`SPR_GROUP_WIDTH'd21: spr_cs = 32'b00000000_00100000_00000000_00000000;
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`SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
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`SPR_GROUP_WIDTH'd22: spr_cs = 32'b00000000_01000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd23: spr_cs = 32'b00000000_10000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd24: spr_cs = 32'b00000001_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd25: spr_cs = 32'b00000010_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd26: spr_cs = 32'b00000100_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd27: spr_cs = 32'b00001000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd28: spr_cs = 32'b00010000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd29: spr_cs = 32'b00100000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd30: spr_cs = 32'b01000000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd31: spr_cs = 32'b10000000_00000000_00000000_00000000;
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`SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
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endcase
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endcase
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//
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//
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// SPRs System Group
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// SPRs System Group
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//
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//
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr = (branch_op == `BRANCHOP_RFE) ? esr : dat_i[`SR_WIDTH-1:0];
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assign to_sr = (branch_op == `BRANCHOP_RFE) ? esr : spr_dataout[`SR_WIDTH-1:0];
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//
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//
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// Selects for system SPRs
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// Selects for system SPRs
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//
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//
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assign cfgr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:4] == `SPR_CFGR));
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assign cfgr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:4] == `SPR_CFGR));
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assign sr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_SR));
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assign rf_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:5] == `SPR_RF));
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assign epcr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_EPCR));
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assign sr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_SR));
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assign eear_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_EEAR));
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assign epcr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EPCR));
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assign esr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[6:0] == `SPR_ESR));
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assign eear_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_EEAR));
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assign esr_sel = (spr_cs[`SPR_GROUP_SYS] && (spr_addr[10:0] == `SPR_ESR));
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//
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//
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// Write enables for system SPRs
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// Write enables for system SPRs
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//
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//
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assign sr_we = (write_spr && sr_sel) | (branch_op == `BRANCHOP_RFE);
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assign sr_we = (write_spr && sr_sel) | (branch_op == `BRANCHOP_RFE);
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| Line 213... |
Line 250... |
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//
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//
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// Output from system SPRs
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// Output from system SPRs
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//
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//
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assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
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assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
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(sr & {32{read_spr & sr_sel}}) |
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(spr_dat_rf & {32{read_spr & rf_sel}}) |
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({{32-`SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
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(epcr & {32{read_spr & epcr_sel}}) |
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(epcr & {32{read_spr & epcr_sel}}) |
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(eear & {32{read_spr & eear_sel}}) |
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(eear & {32{read_spr & eear_sel}}) |
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(esr & {32{read_spr & esr_sel}});
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({{32-`SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
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//
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//
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// Supervision register
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// Supervision register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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| Line 232... |
Line 270... |
$display(" INFO: exception started. SR[SUPV] set and SR[EXR] cleared.");
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$display(" INFO: exception started. SR[SUPV] set and SR[EXR] cleared.");
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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sr[`SR_SUPV] <= #1 1'b1;
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sr[`SR_SUPV] <= #1 1'b1;
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sr[`SR_EXR] <= #1 1'b0;
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sr[`SR_EXR] <= #1 1'b0;
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sr[`SR_WIDTH:2] <= #1 {`SR_WIDTH-2{1'b0}};
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end
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end
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else if (sr_we) begin
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else if (sr_we) begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display(" INFO: writing into SR register: %h", dat_i);
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$display(" INFO: writing into SR register: %h", spr_dataout);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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sr <= #1 to_sr;
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sr <= #1 to_sr;
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end
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end
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//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(alu_op or spr_addr or dat_i or sys_data or spr_dat_pic or spr_dat_pm or spr_dat_dmmu or spr_dat_tt) begin
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always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_pic or spr_dat_pm or
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case (alu_op) // synopsys full_case parallel_case
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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case (sprs_op) // synopsys full_case parallel_case
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`ALUOP_MTSR : begin
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`ALUOP_MTSR : begin
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
|
// synopsys translate_off
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$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, dat_i);
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$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, spr_dataout);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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write_spr = 1'b1;
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write_spr = 1'b1;
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read_spr = 1'b0;
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read_spr = 1'b0;
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to_wbmux = 32'b0;
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to_wbmux = 32'b0;
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| Line 267... |
Line 307... |
to_wbmux = spr_dat_pic;
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to_wbmux = spr_dat_pic;
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`SPR_GROUP_PM:
|
`SPR_GROUP_PM:
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to_wbmux = spr_dat_pm;
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to_wbmux = spr_dat_pm;
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`SPR_GROUP_DMMU:
|
`SPR_GROUP_DMMU:
|
to_wbmux = spr_dat_dmmu;
|
to_wbmux = spr_dat_dmmu;
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`SPR_GROUP_IMMU:
|
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to_wbmux = spr_dat_immu;
|
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`SPR_GROUP_DU:
|
|
to_wbmux = spr_dat_du;
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`SPR_GROUP_SYS:
|
`SPR_GROUP_SYS:
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to_wbmux = sys_data;
|
to_wbmux = sys_data;
|
default:
|
default:
|
to_wbmux = 32'b0;
|
to_wbmux = 32'b0;
|
endcase
|
endcase
|
