| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2001/08/09 13:39:33 lampret
|
|
// Major clean-up.
|
|
//
|
// Revision 1.2 2001/07/22 03:31:54 lampret
|
// Revision 1.2 2001/07/22 03:31:54 lampret
|
// Fixed RAM's oen bug. Cache bypass under development.
|
// Fixed RAM's oen bug. Cache bypass under development.
|
//
|
//
|
// Revision 1.1 2001/07/20 00:46:23 lampret
|
// Revision 1.1 2001/07/20 00:46:23 lampret
|
// Development version of RTL. Libraries are missing.
|
// Development version of RTL. Libraries are missing.
|
//
|
//
|
//
|
//
|
|
|
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
|
// synopsys translate_on
|
`include "defines.v"
|
`include "defines.v"
|
|
|
module wb_biu(
|
module wb_biu(
|
// WISHBONE interface
|
// WISHBONE interface
|
wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
|
wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,
|
| Line 93... |
Line 98... |
output biu_rdy; // data valid
|
output biu_rdy; // data valid
|
output [dw-1:0] biu_from_biu; // output data bus
|
output [dw-1:0] biu_from_biu; // output data bus
|
input [3:0] biu_sel; // byte select inputs
|
input [3:0] biu_sel; // byte select inputs
|
|
|
//
|
//
|
|
// Registers
|
|
//
|
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
reg [aw-1:0] wb_adr_o; // address bus outputs
|
|
reg wb_stb_o; // strobe output
|
|
reg wb_we_o; // indicates write transfer
|
|
reg [3:0] wb_sel_o; // byte select outputs
|
|
reg [dw-1:0] wb_dat_o; // output data bus
|
|
`endif
|
|
|
|
//
|
// WISHBONE I/F <-> Internal RISC I/F conversion
|
// WISHBONE I/F <-> Internal RISC I/F conversion
|
//
|
//
|
|
|
//
|
//
|
// Address bus
|
// Address bus
|
//
|
//
|
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
wb_adr_o <= #1 {aw{1'b0}};
|
|
else
|
|
wb_adr_o <= #1 biu_addr;
|
|
`else
|
assign wb_adr_o = biu_addr;
|
assign wb_adr_o = biu_addr;
|
|
`endif
|
|
|
//
|
//
|
// Input data bus
|
// Input data bus
|
//
|
//
|
assign biu_from_biu = wb_dat_i;
|
assign biu_from_biu = wb_dat_i;
|
|
|
//
|
//
|
// Output data bus
|
// Output data bus
|
//
|
//
|
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
wb_dat_o <= #1 {dw{1'b0}};
|
|
else
|
|
wb_dat_o <= #1 biu_to_biu;
|
|
`else
|
assign wb_dat_o = biu_to_biu;
|
assign wb_dat_o = biu_to_biu;
|
|
`endif
|
|
|
//
|
//
|
// Acknowledgment of the data to the RISC
|
// Acknowledgment of the data to the RISC
|
//
|
//
|
assign biu_rdy = wb_ack_i;
|
assign biu_rdy = wb_ack_i;
|
| Line 124... |
Line 156... |
assign wb_cyc_o = wb_stb_o;
|
assign wb_cyc_o = wb_stb_o;
|
|
|
//
|
//
|
// WB stb_o
|
// WB stb_o
|
//
|
//
|
assign wb_stb_o = biu_read | biu_write;
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
wb_stb_o <= #1 1'b0;
|
|
else
|
|
wb_stb_o <= #1 (biu_read | biu_write);
|
|
`else
|
|
assign wb_stb_o = (biu_read | biu_write);
|
|
`endif
|
|
|
//
|
//
|
// WB we_o
|
// WB we_o
|
//
|
//
|
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
wb_we_o <= #1 1'b0;
|
|
else
|
|
wb_we_o <= #1 biu_write;
|
|
`else
|
assign wb_we_o = biu_write;
|
assign wb_we_o = biu_write;
|
|
`endif
|
|
|
//
|
//
|
// WB sel_o
|
// WB sel_o
|
//
|
//
|
|
`ifdef OR1200_REGISTERED_OUTPUTS
|
|
always @(posedge wb_clk_i or posedge wb_rst_i)
|
|
if (wb_rst_i)
|
|
wb_sel_o <= #1 4'b0000;
|
|
else
|
|
wb_sel_o <= #1 biu_sel;
|
|
`else
|
assign wb_sel_o = biu_sel;
|
assign wb_sel_o = biu_sel;
|
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
