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Rev 161	Rev 168
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/07/20 00:46:23 lampret`
	`// Development version of RTL. Libraries are missing.`
	`//`
`//`	`//`

`include "general.h"	`include "timescale.v"
	`include "defines.v"

`module wbmux(clk, rst, pipeline_freeze, rfwb_op, muxin_a, muxin_b, muxin_c, muxin_d, muxout, muxreg, muxreg_valid);`	`module wbmux(`
	`// Clock and reset`
	`clk, rst,`

	`// Internal i/f`
	`pipeline_freeze, rfwb_op,`
	`muxin_a, muxin_b, muxin_c, muxin_d,`
	`muxout, muxreg, muxreg_valid`
	`);`

parameter width = `OPERAND_WIDTH;	parameter width = `OPERAND_WIDTH;

	`//`
	`// I/O`
	`//`

	`//`
	`// Clock and reset`
	`//`
`input clk;`	`input clk;`
`input rst;`	`input rst;`

	`//`
	`// Internal i/f`
	`//`
`input pipeline_freeze;`	`input pipeline_freeze;`
input [`RFWBOP_WIDTH-1:0] rfwb_op;	input [`RFWBOP_WIDTH-1:0] rfwb_op;
`input [width-1:0] muxin_a;`	`input [width-1:0] muxin_a;`
`input [width-1:0] muxin_b;`	`input [width-1:0] muxin_b;`
`input [width-1:0] muxin_c;`	`input [width-1:0] muxin_c;`
`input [width-1:0] muxin_d;`	`input [width-1:0] muxin_d;`

`output [width-1:0] muxout;`	`output [width-1:0] muxout;`
`output [width-1:0] muxreg;`	`output [width-1:0] muxreg;`
`output muxreg_valid;`	`output muxreg_valid;`

	`//`
	`// Internal wires and regs`
	`//`
`reg [width-1:0] muxout;`	`reg [width-1:0] muxout;`
`reg [width-1:0] muxreg;`	`reg [width-1:0] muxreg;`
`reg muxreg_valid;`	`reg muxreg_valid;`

	`//`
	`// Registered output from the write-back multiplexer`
	`//`
`always @(posedge clk or posedge rst) begin`	`always @(posedge clk or posedge rst) begin`
`if (rst) begin`	`if (rst) begin`
`muxreg <= #1 32'd0;`	`muxreg <= #1 32'd0;`
`muxreg_valid <= #1 1'b0;`	`muxreg_valid <= #1 1'b0;`
`end`	`end`
Line 78...	Line 106...
`muxreg <= #1 muxout;`	`muxreg <= #1 muxout;`
`muxreg_valid <= #1 rfwb_op[0];`	`muxreg_valid <= #1 rfwb_op[0];`
`end`	`end`
`end`	`end`

	`//`
	`// Write-back multiplexer`
	`//`
`always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin`	`always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin`
case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux	case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux
`'b00: muxout <= #1 muxin_a;`	`'b00: muxout <= #1 muxin_a;`
`'b01: begin`	`'b01: begin`
`muxout <= #1 muxin_b;`	`muxout <= #1 muxin_b;`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [wbmux.v] - Diff between revs 161 and 168