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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [wbmux.v] - Diff between revs 205 and 209

Rev 205	Rev 209
Line 116...	Line 116...
`//`	`//`
`// Write-back multiplexer`	`// Write-back multiplexer`
`//`	`//`
`always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin`	`always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin`
case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux	case(rfwb_op[`RFWBOP_WIDTH-1:1]) // synopsys full_case parallel_case infer_mux
`'b00: muxout = muxin_a;`	`2'b00: muxout = muxin_a;`
`'b01: begin`	`2'b01: begin`
`muxout = muxin_b;`	`muxout = muxin_b;`
`ifdef OR1200_VERBOSE	`ifdef OR1200_VERBOSE
`// synopsys translate_off`	`// synopsys translate_off`
`$display(" WBMUX: muxin_b %h", muxin_b);`	`$display(" WBMUX: muxin_b %h", muxin_b);`
`// translate_on`	`// synopsys translate_on`
`endif	`endif
`end`	`end`
`'b10: begin`	`2'b10: begin`
`muxout = muxin_c;`	`muxout = muxin_c;`
`ifdef OR1200_VERBOSE	`ifdef OR1200_VERBOSE
`// synopsys translate_off`	`// synopsys translate_off`
`$display(" WBMUX: muxin_c %h", muxin_c);`	`$display(" WBMUX: muxin_c %h", muxin_c);`
`// translate_on`	`// synopsys translate_on`
`endif	`endif
`end`	`end`
`'b11: begin`	`2'b11: begin`
`muxout = muxin_d + 4'h8;`	`muxout = muxin_d + 4'h8;`
`ifdef OR1200_VERBOSE	`ifdef OR1200_VERBOSE
`// synopsys translate_off`	`// synopsys translate_off`
`$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);`	`$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);`
`// translate_on`	`// synopsys translate_on`
`endif	`endif
`end`	`end`
`endcase`	`endcase`
`end`	`end`