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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 631 |
Rev 638 |
Line 75... |
Line 75... |
int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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extern int mem_cycles;
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/* ICache simulation enabled/disabled. */
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/* ICache simulation enabled/disabled. */
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)))
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if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci)
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return evalsim_mem32(fetchaddr);
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return evalsim_mem32(fetchaddr);
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/* Which set to check out? */
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/* Which set to check out? */
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set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
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set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
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tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
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tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
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Line 111... |
Line 111... |
minway = i;
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minway = i;
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for (i = 0; i < (config.ic.blocksize); i += 4) {
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for (i = 0; i < (config.ic.blocksize); i += 4) {
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ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
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ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
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evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
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evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
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if(!cur_area)
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if(!cur_area) {
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ic[set].way[minway].tagaddr = -1;
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ic[set].way[minway].lru = 0;
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return 0;
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return 0;
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}
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}
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}
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ic[set].way[minway].tagaddr = tagaddr;
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ic[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.ic.nways; i++)
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for (i = 0; i < config.ic.nways; i++)
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if (ic[set].way[i].lru)
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if (ic[set].way[i].lru)
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ic[set].way[i].lru--;
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ic[set].way[i].lru--;
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