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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "spr_defs.h"
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typedef unsigned long sprword;
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typedef unsigned long sprword;
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/* Prototypes */
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/* Prototypes */
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void mtspr(int regno, sprword value);
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void mtspr(int regno, sprword value);
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sprword mfspr(int regno);
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sprword mfspr(int regno);
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void setsprbit(int regno, int bitnum, unsigned long bitvalue);
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void setsprbit(int regno, int bitnum, unsigned long bitvalue);
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int getsprbit(int regno, int bitnum);
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int getsprbit(int regno, int bitnum);
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void sprs_status();
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void sprs_status();
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/* Definition of special-purpose registers (SPRs) */
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#define MAX_GRPS 32
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#define MAX_SPRS_PER_GRP 0x1000
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#define MAX_SPRS (MAX_GRPS * 0x1000000 / MAX_SPRS_PER_GRP)
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/* Base addresses for the groups */
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#define SPRGROUP_SYS 0x00000000
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#define SPRGROUP_DMMU 0x01000000
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#define SPRGROUP_IMMU 0x02000000
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#define SPRGROUP_DC 0x03000000
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#define SPRGROUP_IC 0x04000000
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#define SPRGROUP_MAC 0x05000000
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/* System control and status group */
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#define SPR_VR (SPRGROUP_SYS + 0)
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#define SPR_MPR (SPRGROUP_SYS + 1)
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#define SPR_SR (SPRGROUP_SYS + 2)
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#define SPR_CCR (SPRGROUP_SYS + 3)
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#define SPR_EPCR_BASE (SPRGROUP_SYS + 16)
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#define SPR_EPCR_LAST (SPRGROUP_SYS + 31)
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#define SPR_CTR_BASE (SPRGROUP_SYS + 32)
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#define SPR_CTR_LAST (SPRGROUP_SYS + 47)
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#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
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#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
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/* Data MMU group */
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#define SPR_DTLBMR_BASE (SPRGROUP_DMMU + 0)
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#define SPR_DTLBMR_LAST (SPRGROUP_DMMU + 255)
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#define SPR_DTLBTR_BASE (SPRGROUP_DMMU + 256)
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#define SPR_DTLBTR_LAST (SPRGROUP_DMMU + 511)
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#define SPR_DMMUCR (SPRGROUP_DMMU + 512)
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/* Instruction MMU group */
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#define SPR_ITLBMR_BASE (SPRGROUP_IMMU + 0)
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#define SPR_ITLBMR_LAST (SPRGROUP_IMMU + 255)
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#define SPR_ITLBTR_BASE (SPRGROUP_IMMU + 256)
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#define SPR_ITLBTR_LAST (SPRGROUP_IMMU + 511)
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#define SPR_IMMUCR (SPRGROUP_IMMU + 512)
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/* Data cache group */
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#define SPR_DCR_BASE (SPRGROUP_DC + 0)
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#define SPR_DCR_LAST (SPRGROUP_DC + 511)
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#define SPR_DCCR (SPRGROUP_DC + 512)
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/* Instruction cache group */
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#define SPR_ICR_BASE (SPRGROUP_IC + 0)
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#define SPR_ICR_LAST (SPRGROUP_IC + 511)
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#define SPR_ICCR (SPRGROUP_IC + 512)
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/* MAC group */
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#define SPR_MACLO (SPRGROUP_MAC + 1)
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#define SPR_MACHI (SPRGROUP_MAC + 2)
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/*
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* Bit definitions for the Version Register
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*
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*/
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#define SPR_VR_VER 0xffff0000 /* Processor version */
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#define SPR_VR_PT 0x0000f000 /* Predefined template */
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#define SPR_VR_REV 0x0000003f /* Processor revision */
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/*
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* Bit definitions for the Module Present Register
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*
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*/
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#define SPR_MPR_SYS 0x00000001 /* System control and status module */
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#define SPR_MPR_DMMU 0x00000002 /* Data MMU module */
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#define SPR_MPR_IMMU 0x00000004 /* Instruction MMU module */
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#define SPR_MPR_DC 0x00000008 /* Data cache module */
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#define SPR_MPR_IC 0x00000010 /* Instruction cache module */
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#define SPR_MPR_MAC 0x00000020 /* MAC module */
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#define SPR_MPR_RES 0xffffffc0 /* Custom and future modules */
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/*
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* Bit definitions for the Supervision Register
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*
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*/
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#define SPR_SR_CID 0xf0000000 /* Context ID */
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#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
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#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
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#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
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#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
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#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
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#define SPR_SR_EIR 0x00000004 /* External Interrupt Recognition */
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#define SPR_SR_EXR 0x00000002 /* Exception Recognition */
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#define SPR_SR_SUPV 0x00000001 /* Supervisor mode */
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/*
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* Bit definitions for the Condition Code Register
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*
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*/
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#define SPR_CCR_OVERFL 0x00000004 /* Overflow */
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#define SPR_CCR_CARRY 0x00000002 /* Carry */
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#define SPR_CCR_FLAG 0x00000001 /* Compare Flag */
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/*
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* Bit definitions for the Data MMU Control Register
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*
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*/
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#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
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#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
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/*
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* Bit definitions for the Instruction MMU Control Register
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*
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*/
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#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
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#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
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#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
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#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
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/*
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* Bit definitions for the Data TLB Match Register
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*
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*/
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#define SPR_DTLBMR_PL1 0x00000001 /* Page Level 1 (if 0 then PL2)*/
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#define SPR_DTLBMR_CID 0x0000001e /* Context ID */
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#define SPR_DTLBMR_VPN 0xfffffc00 /* Virtual Page Number */
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/*
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* Bit definitions for the Data TLB Translate Register
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*
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*/
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#define SPR_DTLBTR_V 0x00000001 /* Valid */
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#define SPR_DTLBTR_CC 0x00000002 /* Cache Coherency */
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#define SPR_DTLBTR_CI 0x00000004 /* Cache Inhibit */
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#define SPR_DTLBTR_WBC 0x00000008 /* Write-Back Cache*/
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#define SPR_DTLBTR_WOM 0x00000010 /* Weakly-Ordered Memory */
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#define SPR_DTLBTR_A 0x00000020 /* Accessed */
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#define SPR_DTLBTR_D 0x00000040 /* Dirty */
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#define SPR_DTLBTR_PPI 0x00000380 /* Page Protection Index */
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#define SPR_DTLBTR_PPN 0xfffffc00 /* Physical Page Number */
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/*
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* Bit definitions for the Instruction TLB Match Register
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*
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*/
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#define SPR_ITLBMR_PL1 0x00000001 /* Page Level 1 (if 0 then PL2)*/
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#define SPR_ITLBMR_CID 0x0000001e /* Context ID */
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#define SPR_ITLBMR_VPN 0xfffffc00 /* Virtual Page Number */
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/*
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* Bit definitions for the Instruction TLB Translate Register
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*
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*/
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#define SPR_ITLBTR_V 0x00000001 /* Valid */
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#define SPR_ITLBTR_CC 0x00000002 /* Cache Coherency */
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#define SPR_ITLBTR_CI 0x00000004 /* Cache Inhibit */
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#define SPR_ITLBTR_WBC 0x00000008 /* Write-Back Cache*/
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#define SPR_ITLBTR_WOM 0x00000010 /* Weakly-Ordered Memory */
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#define SPR_ITLBTR_A 0x00000020 /* Accessed */
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#define SPR_ITLBTR_D 0x00000040 /* Dirty */
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#define SPR_ITLBTR_PPI 0x00000380 /* Page Protection Index */
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#define SPR_ITLBTR_PPN 0xfffffc00 /* Physical Page Number */
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