| Line 531... |
Line 531... |
GEN ("\n/* Memory stores */\n");
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GEN ("\n/* Memory stores */\n");
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GEN ("always @(");
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GEN ("always @(");
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for (i = 0; i < f->nmsched; i++)
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for (i = 0; i < f->nmsched; i++)
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if (f->mtype[i] & MT_STORE) {
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if (f->mtype[i] & MT_STORE) {
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char t[30];
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char t[30];
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GEN ("%s%s", cur_store++ ? ", " : "", print_op_v (f, t, f->msched[i], 0));
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GEN ("%s%s", cur_store++ ? " or " : "", print_op_v (f, t, f->msched[i], 0));
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}
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}
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|
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cur_store = 0;
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cur_store = 0;
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GEN (")\nbegin\n");
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GEN (")\nbegin\n");
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for (i = 0; i < f->nmsched; i++)
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for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
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if (f->mtype[i] & MT_STORE) {
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char t[30];
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char t[30];
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GEN (" %sif (s_stb[%i]) swb_dat_o = %s;\n", i ? "else " : "", cur_store++,
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GEN (" %sif (s_stb[%i]) swb_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
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print_op_v (f, t, f->msched[i], 0));
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print_op_v (f, t, f->msched[i], 0));
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cur_store++;
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//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
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//PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
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}
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}
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GEN (" else swb_dat_o = 32'hx;\n");
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GEN ("end\n");
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GEN ("end\n");
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}
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}
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|
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/* Generate load and store state machine */
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/* Generate load and store state machine */
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for (j = 0; j < 2; j++) {
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for (j = 0; j < 2; j++) {
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| Line 562... |
Line 563... |
|| j == 1 && nstores
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|| j == 1 && nstores
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|| j == 2 && ncalls) {
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|| j == 2 && ncalls) {
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int cur = 0;
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int cur = 0;
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char t[30];
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char t[30];
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GEN ("\n/* %s state machine */\n", s);
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GEN ("\n/* %s state machine */\n", s);
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GEN ("always @(posedge clk or posedge rst)\n");
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GEN (" if (rst) %c_stb <= #Tp %i'h0;\n", c, j == 0 ? nloads : j == 1 ? nstores : ncalls);
|
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GEN (" else begin\n");
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for (i = 0; i < f->nmsched; i++)
|
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if (j == 0 && f->mtype[i] & MT_LOAD
|
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|| j == 1 && f->mtype[i] & MT_STORE
|
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|| j == 2 && f->mtype[i] & MT_CALL) {
|
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dep_list *dep = f->INSN(f->msched[i]).dep;
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assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
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GEN (" if (");
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print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
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GEN (") begin\n");
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print_turn_off_dep (fo, f, dep);
|
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GEN (" %c_stb[%i] <= #Tp 1'b1;\n", c, cur++);
|
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GEN (" end\n");
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}
|
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GEN (" if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
|
|
GEN (" end\n");
|
|
|
|
GEN ("\n/* %s state generator machine */\n", s);
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GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < f->nmsched; i++) {
|
for (i = 0; i < f->nmsched; i++) {
|
print_op_v (f, t, f->msched[i], 1); break;
|
print_op_v (f, t, f->msched[i], 1);
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GEN (" or ");
|
GEN ("%s or ", t);
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GEN ("t%x_%x", REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
|
GEN (" or ");
|
|
}
|
}
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
GEN ("bb_start_r");
|
GEN (" or %c_end)\n", c);
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if (nloads) GEN (" or l_end");
|
|
if (nstores) GEN (" or s_end");
|
|
GEN (")\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
cucdebug (1, "%s\n", s);
|
cucdebug (1, "%s\n", s);
|
for (i = 0; i < f->nmsched; i++)
|
for (i = 0; i < f->nmsched; i++)
|
if (j == 0 && f->mtype[i] & MT_LOAD
|
if (j == 0 && f->mtype[i] & MT_LOAD
|
|| j == 1 && f->mtype[i] & MT_STORE
|
|| j == 1 && f->mtype[i] & MT_STORE
|
| Line 583... |
Line 604... |
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
|
GEN (" if (");
|
GEN (" if (");
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
|
GEN (") begin\n");
|
GEN (") begin\n");
|
print_turn_off_dep (fo, f, dep);
|
GEN (" %cwb_cycstb_o = 1'b1;\n", c);
|
GEN (" %c_stb[%i] <= #Tp 1'b1;\n", c, cur++);
|
GEN (" %cwb_sel_o[3:0] = 4'b", c);
|
GEN (" %cwb_cycstb_o <= #Tp 1'b1;\n", c);
|
|
GEN (" %cwb_sel_o[3:0] <= #Tp 4'b", c);
|
|
switch (f->mtype[i] & MT_WIDTH) {
|
switch (f->mtype[i] & MT_WIDTH) {
|
case 1: GEN ("0001 << (%s & 32'h3);\n",
|
case 1: GEN ("0001 << (%s & 32'h3);\n",
|
print_op_v (f, t, f->msched[i], 1)); break;
|
print_op_v (f, t, f->msched[i], 1)); break;
|
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
|
case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
|
print_op_v (f, t, f->msched[i], 1)); break;
|
print_op_v (f, t, f->msched[i], 1)); break;
|
case 4: GEN ("1111;\n"); break;
|
case 4: GEN ("1111;\n"); break;
|
default: assert (0);
|
default: assert (0);
|
}
|
}
|
GEN (" %cwb_linbrst_o <= #Tp 1'b%i;\n", c,
|
GEN (" %cwb_linbrst_o = 1'b%i;\n", c,
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
(f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
|
GEN (" %cwb_adr_o <= #Tp t%x_%x & ~32'h3;\n", c,
|
GEN (" %cwb_adr_o = t%x_%x & ~32'h3;\n", c,
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
|
GEN (" end\n");
|
GEN (" end else ");
|
}
|
}
|
GEN (" if (%c_end[%i]) begin\n", c, cur - 1);
|
GEN (" if (%c_end[%i]) begin\n", c, cur - 1);
|
GEN (" %c_stb <= #Tp %i'h0;\n", c, cur);
|
GEN (" %cwb_cycstb_o = 1'b0;\n", c);
|
GEN (" %cwb_cycstb_o <= #Tp 1'b0;\n", c);
|
GEN (" %cwb_sel_o[3:0] = 4'bx;\n", c);
|
GEN (" %cwb_sel_o[3:0] <= #Tp 4'b0000;\n", c);
|
GEN (" %cwb_linbrst_o = 1'b0;\n", c);
|
GEN (" %cwb_linbrst_o <= #Tp 1'b0;\n", c);
|
GEN (" %cwb_adr_o = 32'hx;\n", c);
|
GEN (" %cwb_adr_o <= #Tp 32'h0;\n", c);
|
GEN (" end else begin\n");
|
|
GEN (" %cwb_cycstb_o = 1'b0;\n", c);
|
|
GEN (" %cwb_sel_o[3:0] = 4'bx;\n", c);
|
|
GEN (" %cwb_linbrst_o = 1'b0;\n", c);
|
|
GEN (" %cwb_adr_o = 32'hx;\n", c);
|
GEN (" end\n");
|
GEN (" end\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
}
|
}
|
|
|
| Line 852... |
Line 875... |
|
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("assign cuc_ack_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
GEN ("assign cuc_ack_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
}
|
}
|
|
|
|
/* Store/load Wishbone bridge */
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++) {
|
char t = j ? 's' : 'l';
|
char t = j ? 's' : 'l';
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
