URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [basic.S] - Diff between revs 432 and 511

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Rev 432	Rev 511
Line 4...	Line 4...
`#define MEM_RAM 0x40000000`	`#define MEM_RAM 0x40000000`

`.section .except`	`.section .except`
`.org 0x100`	`.org 0x100`
`_reset:`	`_reset:`
`l.nop`	`l.nop 0`
`l.movhi r1,hi(_regs)`	`l.movhi r1,hi(_regs)`
`l.ori r1,r1,lo(_regs)`	`l.ori r1,r1,lo(_regs)`
`l.jr r1`	`l.jr r1`
`l.nop`	`l.nop`

Line 46...	Line 46...
`l.sub r19,r20,r13`	`l.sub r19,r20,r13`
`l.sub r18,r19,r14`	`l.sub r18,r19,r14`
`l.sub r17,r18,r15`	`l.sub r17,r18,r15`
`l.sub r16,r17,r16`	`l.sub r16,r17,r16`

`l.mtspr r0,r16,0x1234 /* Should be 0xffff0012 */`	`l.or r3,r0,r16`
	`l.nop NOP_REPORT /* Should be 0xffff0012 */`

`l.movhi r31, hi(MEM_RAM)`	`l.movhi r31, hi(MEM_RAM)`
`l.ori r31,r31, lo(MEM_RAM)`	`l.ori r31,r31, lo(MEM_RAM)`
`l.sw 0(r31),r16`	`l.sw 0(r31),r16`

Line 100...	Line 101...
`l.sh 4(r31),r4`	`l.sh 4(r31),r4`

`l.lwz r4,4(r31)`	`l.lwz r4,4(r31)`
`l.add r8,r8,r4`	`l.add r8,r8,r4`

`l.mtspr r0,r8,0x1234 /* Should be 0x12352af7 */`	`l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0x12352af7 */`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.add r8,r9,r8`	`l.add r8,r9,r8`
`l.sw 0(r31),r8`	`l.sw 0(r31),r8`

Line 123...	Line 125...
`l.add r9,r3,r4`	`l.add r9,r3,r4`
`l.mul r7,r9,r7`	`l.mul r7,r9,r7`
`l.divu r7,r7,r4`	`l.divu r7,r7,r4`
`l.add r8,r8,r7`	`l.add r8,r8,r7`

`l.mtspr r0,r8,0x1234 /* Should be 0x7ffffffe */`	`l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0x7ffffffe */`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.add r8,r9,r8`	`l.add r8,r9,r8`
`l.sw 0(r31),r8`	`l.sw 0(r31),r8`

Line 145...	Line 148...
`l.xor r8,r8,r5`	`l.xor r8,r8,r5`

`l.ori r8,r8,2`	`l.ori r8,r8,2`
`l.or r8,r8,r4`	`l.or r8,r8,r4`

`l.mtspr r0,r8,0x1234 /* Should be 0xffffa5a7 */`	`l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0xffffa5a7 */`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.add r8,r9,r8`	`l.add r8,r9,r8`
`l.sw 0(r31),r8`	`l.sw 0(r31),r8`

Line 167...	Line 171...
`l.srl r8,r8,r4`	`l.srl r8,r8,r4`

`l.srai r8,r8,2`	`l.srai r8,r8,2`
`l.sra r8,r8,r4`	`l.sra r8,r8,r4`

`l.mtspr r0,r8,0x1234 /* Should be 0x000fffff */`	`l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0x000fffff */`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.add r8,r9,r8`	`l.add r8,r9,r8`
`l.sw 0(r31),r8`	`l.sw 0(r31),r8`

Line 378...	Line 383...
`l.sflesi r3,-2`	`l.sflesi r3,-2`
`l.mfspr r5,r0,17`	`l.mfspr r5,r0,17`
`l.andi r4,r5,0x200`	`l.andi r4,r5,0x200`
`l.add r8,r8,r4`	`l.add r8,r8,r4`

`l.mtspr r0,r8,0x1234 /* Should be 0x00002800 */`	`l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0x00002800 */`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.add r8,r9,r8`	`l.add r8,r9,r8`
`l.sw 0(r31),r8`	`l.sw 0(r31),r8`

Line 428...	Line 434...
`l.rfe`	`l.rfe`
`l.addi r8,r8,1 /* l.rfe should not have a delay slot */`	`l.addi r8,r8,1 /* l.rfe should not have a delay slot */`

`l.addi r8,r8,1`	`l.addi r8,r8,1`

`_T7: l.mtspr r0,r8,0x1234 /* Should be 0x000000009 */`	`_T7: l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0x000000009 */`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.add r8,r9,r8`	`l.add r8,r9,r8`
`l.sw 0(r31),r8`	`l.sw 0(r31),r8`

`l.lwz r9,0(r31)`	`l.lwz r9,0(r31)`
`l.movhi r3,0x4c69`	`l.movhi r3,0x4c69`
`l.ori r3,r3,0xe5f7`	`l.ori r3,r3,0xe5f7`
`l.add r8,r8,r3`	`l.add r8,r8,r3`

`l.mtspr r0,r8,0x1234 /* Should be 0xdeaddead */`	`l.or r3,r0,r8`
	`l.nop NOP_REPORT /* Should be 0xdeaddead */`

`l.addi r3,r0,0`	`l.addi r3,r0,0`
`l.sys 203`	`l.nop NOP_EXIT`

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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [basic.S] - Diff between revs 432 and 511