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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [cache.c] - Diff between revs 575 and 621

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Line 1... Line 1...
/* Cache test */
/* Cache test */
#include "support.h"
#include "support.h"
#include "spr_defs.h"
#include "spr_defs.h"
 
 
#define MEM_RAM 0x40100000
#define OR1KSIM 1
 
 
 
#ifdef OR1KSIM
 
#undef  UART
 
#else
 
#define UART 1
 
#endif
 
 
 
#define MEM_RAM 0x00100000
 
 
/* Number of IC sets (power of 2) */
/* Number of IC sets (power of 2) */
#define IC_SETS 512
#define IC_SETS 256
#define DC_SETS 512
#define DC_SETS 256
 
 
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
#define IC_BLOCK_SIZE 16
#define IC_BLOCK_SIZE 16
#define DC_BLOCK_SIZE 16
#define DC_BLOCK_SIZE 16
 
 
Line 23... Line 31...
/* Memory access macros */
/* Memory access macros */
#define REG8(add) *((volatile unsigned char *)(add))
#define REG8(add) *((volatile unsigned char *)(add))
#define REG16(add) *((volatile unsigned short *)(add))
#define REG16(add) *((volatile unsigned short *)(add))
#define REG32(add) *((volatile unsigned long *)(add))
#define REG32(add) *((volatile unsigned long *)(add))
 
 
 
#if UART
 
#include "uart.h"
 
#define IN_CLK  20000000
 
#define UART_BASE  0x9c000000
 
#define UART_BAUD_RATE 9600
 
 
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
 
 
#define WAIT_FOR_XMITR \
 
        do { \
 
                lsr = REG8(UART_BASE + UART_LSR); \
 
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
 
 
#define WAIT_FOR_THRE \
 
        do { \
 
                lsr = REG8(UART_BASE + UART_LSR); \
 
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
 
 
#define CHECK_FOR_CHAR \
 
        (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
 
 
 
#define WAIT_FOR_CHAR \
 
         do { \
 
                lsr = REG8(UART_BASE + UART_LSR); \
 
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
 
 
#define UART_TX_BUFF_LEN 32
 
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
 
 
#define print_n(x)  \
 
  { \
 
    uart_putc(s[((x) >> 28) & 0x0f]); \
 
    uart_putc(s[((x) >> 24) & 0x0f]); \
 
    uart_putc(s[((x) >> 20) & 0x0f]); \
 
    uart_putc(s[((x) >> 16) & 0x0f]); \
 
    uart_putc(s[((x) >> 12) & 0x0f]); \
 
    uart_putc(s[((x) >> 8) & 0x0f]);  \
 
    uart_putc(s[((x) >> 4) & 0x0f]);  \
 
    uart_putc(s[((x) >> 0) & 0x0f]);  \
 
  }
 
 
 
const char s[] = "0123456789abcdef";
 
 
 
void uart_init(void)
 
{
 
        int devisor;
 
 
 
        /* Reset receiver and transmiter */
 
        REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
 
 
        /* Disable all interrupts */
 
        REG8(UART_BASE + UART_IER) = 0x00;
 
 
 
        /* Set 8 bit char, 1 stop bit, no parity */
 
        REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
 
 
        /* Set baud rate */
 
        devisor = IN_CLK/(16 * UART_BAUD_RATE);
 
        REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
 
        REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;
 
        REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;
 
        REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
 
 
 
        return;
 
}
 
 
 
static inline void uart_putc(char c)
 
{
 
        unsigned char lsr;
 
 
 
        WAIT_FOR_THRE;
 
        REG8(UART_BASE + UART_TX) = c;
 
        if(c == '\n') {
 
          WAIT_FOR_THRE;
 
          REG8(UART_BASE + UART_TX) = '\r';
 
        }
 
        WAIT_FOR_XMITR;
 
}
 
 
 
static inline void print_str(char *str)
 
{
 
  while(*str != 0) {
 
    uart_putc(*str);
 
    str++;
 
  }
 
}
 
 
 
static inline char uart_getc()
 
{
 
        unsigned char lsr;
 
        char c;
 
 
 
        WAIT_FOR_CHAR;
 
        c = REG8(UART_BASE + UART_RX);
 
        return c;
 
}
 
#endif
 
 
 
extern void ic_enable(void);
 
extern void ic_disable(void);
 
extern void dc_enable(void);
 
extern void dc_disable(void);
 
extern void dc_inv(void);
 
extern unsigned long ic_inv_test(void);
 
extern unsigned long dc_inv_test(unsigned long);
 
 
extern void (*jalr)(void);
extern void (*jalr)(void);
extern void (*jr)(void);
extern void (*jr)(void);
 
 
/* Index on jump table */
/* Index on jump table */
unsigned long jump_indx;
unsigned long jump_indx;
Line 53... Line 167...
        /* Load next executin address from table */
        /* Load next executin address from table */
        asm("l.lwz\t\tr3,0(r3)");
        asm("l.lwz\t\tr3,0(r3)");
        /* Jump to that address */
        /* Jump to that address */
        asm("l.jr\t\tr3") ;
        asm("l.jr\t\tr3") ;
        /* Report that we succeeded */
        /* Report that we succeeded */
        asm("l.nop\t2");
        asm("l.nop\t0");
}
}
 
 
void copy_jr(unsigned long add)
void copy_jr(unsigned long add)
{
{
        memcpy((void *)add, (void *)&jr, 24);
        memcpy((void *)add, (void *)&jr, 24);
Line 69... Line 183...
  asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
  asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
        asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");
        asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");
        asm("l.nop" : :);
        asm("l.nop" : :);
}
}
 
 
void icache_enable(void)
 
{
 
        unsigned long add;
 
 
 
        /* First invalidate the cache. As at this point cache is disabled,
 
           the cache acts as it contains image of lowest memory block */
 
        for(add = 1; add <= IC_SIZE; add += IC_BLOCK_SIZE)
 
                mtspr(SPR_ICBIR, add);
 
 
 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
 
}
 
 
 
void dcache_enable(void)
 
{
 
        unsigned long add;
 
 
 
        /* First invalidate the cache. As at this point cache is disabled,
 
           the cache acts as it contains image of lowest memory block */
 
        for(add = 1; add <= DC_SIZE; add += DC_BLOCK_SIZE)
 
                mtspr(SPR_DCBIR, add);
 
 
 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
 
}
 
 
 
void icache_disable(void)
 
{
 
 
 
        /* This is write trough cache so we dont have to flush it */
 
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
 
}
 
 
 
void dcache_disable(void)
 
{
 
 
 
        /* This is write trough cache so we dont have to flush it */
 
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
 
}
 
 
 
int dc_test(void)
int dc_test(void)
{
{
        int i;
        int i;
        unsigned long base, add, ul;
        unsigned long base, add, ul;
 
 
        base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
        base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
 
 
        dcache_enable();
        dc_enable();
 
 
        /* Cache miss r */
        /* Cache miss r */
        add = base;
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
        for(i = 0; i < DC_WAYS; i++) {
                ul = REG32(add);
                ul = REG32(add);
                ul = REG32(add + DC_BLOCK_SIZE);
                ul = REG32(add + DC_BLOCK_SIZE + 4);
                ul = REG32(add + 2*DC_BLOCK_SIZE);
                ul = REG32(add + 2*DC_BLOCK_SIZE + 8);
                ul = REG32(add + 3*DC_BLOCK_SIZE);
                ul = REG32(add + 3*DC_BLOCK_SIZE + 12);
                add += DC_SETS*DC_BLOCK_SIZE;
                add += DC_SETS*DC_BLOCK_SIZE;
        }
        }
 
 
        /* Cache hit w */
        /* Cache hit w */
        add = base;
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
        for(i = 0; i < DC_WAYS; i++) {
                REG32(add + 0) = 0x00000001;
                REG32(add + 0) = 0x00000001;
 
                REG32(add + 4) = 0x00000000;
 
                REG32(add + 8) = 0x00000000;
 
                REG32(add + 12) = 0x00000000;
 
                REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
                REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
 
                REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000;
 
                REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000;
 
                REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000;
 
                REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
                REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
 
                REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000;
 
                REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000;
 
                REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000;
 
                REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
                REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
                add += DC_SETS*DC_BLOCK_SIZE;
                add += DC_SETS*DC_BLOCK_SIZE;
        }
        }
 
 
        /* Cache hit r/w */
        /* Cache hit r/w */
Line 185... Line 273...
                        REG16(add+ DC_BLOCK_SIZE - 16) +
                        REG16(add+ DC_BLOCK_SIZE - 16) +
                        REG16(add + 2*DC_BLOCK_SIZE + 14);
                        REG16(add + 2*DC_BLOCK_SIZE + 14);
                add += DC_SETS*DC_BLOCK_SIZE;
                add += DC_SETS*DC_BLOCK_SIZE;
        }
        }
 
 
        dcache_disable();
        dc_disable();
 
 
        return ul;
        return ul;
}
}
 
 
int ic_test(void)
int ic_test(void)
Line 241... Line 329...
 
 
        /* Go home */
        /* Go home */
        jump_add[15*i] = (unsigned long)&jalr;
        jump_add[15*i] = (unsigned long)&jalr;
 
 
        /* Initilalize table index */
        /* Initilalize table index */
        jump_indx = &jump_add[0];
        jump_indx = (unsigned long)&jump_add[0];
 
 
        icache_enable();
        ic_enable();
 
 
        /* Go */
        /* Go */
        call(base);
        call(base);
 
 
        icache_disable();
        ic_disable();
 
 
        return 0xdeaddead;
        return 0;
}
}
 
 
int main(void)
int main(void)
{
{
        int rc;
        unsigned long rc, ret = 0;
 
 
 
#ifdef UART
 
  /* Initialize controller */
 
  uart_init();
 
#endif
 
 
 
#ifdef UART
 
  print_str("DC test :            ");
 
#endif
        rc = dc_test();
        rc = dc_test();
 
  ret += rc;
 
#ifdef UART
 
  print_n(rc+0xdeaddca1);
 
  print_str("\n");
 
#else
        report(rc + 0xdeaddca1);
        report(rc + 0xdeaddca1);
 
#endif
 
 
        /* Be aware that this test doesn't report result troug report call.
#ifndef OR1KSIM
           It writes to spr 0x1234 directly (in jump function)!!!
#ifdef UART
 
  print_str("DC invalidate test : ");
           This test can not be run on or1ksim. */
#endif
 
        rc = dc_inv_test(MEM_RAM);
 
  ret += rc;
 
#ifdef UART
 
  print_n(rc + 0x9e8daa91);
 
  print_str("\n");
 
#else
 
        report(rc + 0x9e8daa91);
 
#endif
 
#endif
 
 
 
#ifdef UART
 
  print_str("IC test :            ");
 
#endif
        rc = ic_test();
        rc = ic_test();
        report(rc);
  ret += rc;
 
#ifdef UART
 
  print_n(rc + 0xdeaddead);
 
  print_str("\n");
 
#else
 
        report(rc + 0xdeaddead);
 
#endif
 
 
 
 
 
#ifndef OR1KSIM
 
#ifdef UART
 
  print_str("IC invalidate test : ");
 
#endif
 
  ic_enable();
 
  rc = ic_inv_test();
 
  ret += rc;
 
#ifdef UART
 
  print_n(rc + 0xdeadde8f);
 
  print_str("\n");
 
  while(1);
 
#else
 
        report(rc + 0xdeadde8f);
 
#endif
 
#endif
 
 
 
 
 
        report(ret + 0xdeaddca1);
        exit(0);
        exit(0);
 
 
        return 0;
        return 0;
}
}
 
 

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