URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [tick/] [tick.c] - Diff between revs 189 and 332

Rev 189	Rev 332
Line 34...	Line 34...
`int tt_stopped = 0;`	`int tt_stopped = 0;`

`/* Reset. It initializes TTCR register. */`	`/* Reset. It initializes TTCR register. */`
`void tick_reset()`	`void tick_reset()`
`{`	`{`
	`if (config.tick.enabled) {`
	`if (config.sim.verbose)`
`printf("Resetting Tick Timer.\n");`	`printf("Resetting Tick Timer.\n");`
`mtspr(SPR_TTCR, 0);`	`mtspr(SPR_TTCR, 0);`
`mtspr(SPR_TTMR, 0);`	`mtspr(SPR_TTMR, 0);`
`tt_stopped = 0;`	`tt_stopped = 0;`
	`} else`
	`tt_stopped = 1;`
`}`	`}`

`/* Simulation hook. Must be called every clock cycle to simulate tick`	`/* Simulation hook. Must be called every clock cycle to simulate tick`
`timer. It does internal functional tick timer simulation. */`	`timer. It does internal functional tick timer simulation. */`
`void tick_clock()`	`inline void tick_clock()`
`{`	`{`
`unsigned long ttcr;`	`unsigned long ttcr;`
`unsigned long ttmr;`	`unsigned long ttmr;`

	`if (tt_stopped)`
	`return;`

`ttcr = mfspr(SPR_TTCR);`	`ttcr = mfspr(SPR_TTCR);`
`ttmr = mfspr(SPR_TTMR);`	`ttmr = mfspr(SPR_TTMR);`

`if (!(ttmr & SPR_TTMR_M) \|\| tt_stopped)`	`if (!(ttmr & SPR_TTMR_M))`
`return;`	`return;`

`if ((ttcr & SPR_TTCR_PERIOD) == (ttmr & SPR_TTMR_PERIOD)) {`	`if ((ttcr & SPR_TTCR_PERIOD) == (ttmr & SPR_TTMR_PERIOD)) {`
`int mode = (ttmr & SPR_TTMR_M) >> 30; /* CZ 04/09/01 */`	`int mode = (ttmr & SPR_TTMR_M) >> 30; /* CZ 04/09/01 */`