OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [Makefile.am] - Diff between revs 30 and 92

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 30 Rev 92
Line 2... Line 2...
#
#
#
#
#
#
#
#
 
 
SUBDIRS = cpu bpb support cache mmu peripheral
SUBDIRS = cpu bpb support cache mmu peripheral tick
 
 
noinst_PROGRAMS = sim
noinst_PROGRAMS = sim
 
 
sim_SOURCES     = toplevel.c sim-config.c
sim_SOURCES     = toplevel.c sim-config.c
sim_LDADD       = cpu/common/libcommon.a cpu/$(CPU_ARCH)/libarch.a \
sim_LDADD       = cpu/common/libcommon.a cpu/$(CPU_ARCH)/libarch.a \
        cpu/or1k/libor1k.a support/libsupport.a mmu/libmmu.a \
        cpu/or1k/libor1k.a support/libsupport.a mmu/libmmu.a \
        bpb/libbpb.a cache/libcache.a peripheral/libperipheral.a
        bpb/libbpb.a cache/libcache.a peripheral/libperipheral.a \
 
        tick/libtick.a
sim_LDFLAGS     = -lreadline
sim_LDFLAGS     = -lreadline

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.