URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [README] - Diff between revs 21 and 54

Rev 21	Rev 54
Line 52...	Line 52...

`Issue 'sim testbench/dhry.or32' or 'sim testbench/dhry.dlx' to`	`Issue 'sim testbench/dhry.or32' or 'sim testbench/dhry.dlx' to`
`test simulator. See testbench/README for details about Dhrystone 2.1`	`test simulator. See testbench/README for details about Dhrystone 2.1`
`benchmark.`	`benchmark.`

	`For microkernel test (exception test) undefine ONLY_VIRTUAL_MACHINE (you want`
	`exceptions, right !) in cpu/or1k/except.h and recompile simulator. A compiled`
	`and linked version should already exist in testbench/uos. Just issue`
	`'sim testbench/uos/uos.or32' from the top level sim directory. Currently only`
	`OR32 is supported by UOS.`

`OpenRISC and open cores`	`OpenRISC and open cores`
`=======================`	`=======================`

`About the same idea as with GNU project except we want free and open source`	`About the same idea as with GNU project except we want free and open source`
`IP (intellectual property) cores. We design open source, synthesizable`	`IP (intellectual property) cores. We design open source, synthesizable`