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What is this stuff?
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What is this stuff?
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===================
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===================
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This is OpenRISC 1000 and DLX architectural simulator. It was written by
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This is OpenRISC 1000 architectural simulator. See the file COPYING
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Damjan Lampret and it is free software. See the file COPYING for copying
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for copying permission. To contact the authors, see AUTHORS file.
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permission. To contact the author, send mail to .
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I use it to define OR1K system architecture. An implementation simulator
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for OR1K will be also available, probably in Mar/2000 or later.
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Initially this software was not meant to be released to public because it
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was developed just to analyze program flow of GCC generated assembly code.
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With the time it became bigger and was able to generate statistics about
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superscalar issuing of multiple instructions. I've used it as a test simulator
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to test OR1K GCC port. Perhaps some day I will (or perhaps someone else would
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like to do that ??) clean-up the code and reorganize it.
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This simulator loads an assembly file for one of the both architectures
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This simulator loads an assembly file for one of the both architectures
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and it simulates the operation of instructions. Because it was meant to be used
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and it simulates the operation of instructions.
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only to test characteristics of various RISC architectures and various GCC
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optimization methods, it has a bit strange memory model. It is abstract and
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physical at the same time. I can't really explain, just check the sources if
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interested. Some other things are strange or incomplete too (like
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C library emulation, currently supports only printf via simprintf).
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MMU directory is not functional. Someday it will be filled with code for
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virtual memory simulation.
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Installation
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Installation
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============
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============
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To compile, run the configure script and specify the target architecture.
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To compile, run the configure script and specify the target architecture.
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After that, just issue "make all" command. By default there should be no
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After that, just issue "make all" command. By default there should be no
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warnings. There is no "make install". Just use it from default location
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warnings. There is no "make install". Just use it from default location
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or copy it to your bin directory (usually something like /usr/local/bin
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or copy it to your bin directory (usually something like /usr/local/bin
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or ~/bin).
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or ~/bin).
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This program hasn't been written with security in mind. It has many static
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buffers and it does not check the size of input strings (user commands
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or whatever). So don't setuid it. If it kills your dog, don't blame it on me.
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To select DLX simulation, change the target to the configure script to 'dlx'
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and recompile everything (do 'make all' again).
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GNU Tools
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GNU Tools
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=========
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=========
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To build GNU tools:
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Instructions how to build GNU tools can be found on www.opencores.org
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cvs -d :pserver:cvs@cvs.opencores.org:/home/oc/cvs -z9 co -d work or1k
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mkdir b-b
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cd b-b
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../binutils/configure --target=or32-rtems --prefix=/opt/or32-rtems &&
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make all install
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export PATH=/opt/or32-rtems/bin:$PATH
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cd ../gcc
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./contrib/egcs_update --touch
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ln -s ../newlib/newlib .
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cd ..
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mkdir b-gcc
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cd b-gcc
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../gcc/configure --target=or32-rtems \
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--with-gnu-as --with-gnu-ld --with-newlib --verbose \
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--enable-threads --prefix=/opt/or32-rtems --enable-languages="c" &&
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\
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make all install
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Simulator test
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Simulator test
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==============
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==============
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Edit the sim.cfg file in order to configure your system.
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Issue 'sim testbench/dhry.or32' or 'sim testbench/dhry.dlx' to
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Issue 'sim testbench/dhry.or32' or 'sim testbench/dhry.dlx' to
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test simulator. See testbench/README for details about Dhrystone 2.1
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test simulator. See testbench/README for more details about running.
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benchmark.
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For microkernel test (exception test) undefine ONLY_VIRTUAL_MACHINE (you want
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Also run sim with --help option for list of command line options and
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exceptions, right !) in cpu/or1k/except.h and recompile simulator. A compiled
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help in command mode, to list the commands.
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and linked version should already exist in testbench/uos. Just issue
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'sim testbench/uos/uos.or32' from the top level sim directory. Currently only
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OR32 is supported by UOS.
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OpenRISC and open cores
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OpenRISC and open cores
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=======================
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=======================
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About the same idea as with GNU project except we want free and open source
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About the same idea as with GNU project except we want free and open source
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IP (intellectual property) cores. We design open source, synthesizable
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IP (intellectual property) cores. We design open source, synthesizable
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cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that
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cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that
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will run GNU/Linux.
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will run GNU/Linux.
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For more information visit us at http://www.opencores.org.
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For more information visit us at http://www.opencores.org.
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--
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29/Feb/2000, Damjan Lampret email:lampret@opencores.org
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03/Mar/2000, Johan Rydberg email:johan.rydberg@netinsight.net
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04/May/2000, Jimmy Chen-Min Chen email:jimmy@ee.nctu.edu.tw
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