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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cache/] [dcache_model.c] - Diff between revs 1085 and 1308

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Rev 1085 Rev 1308
Line 96... Line 96...
      except_handle(EXCEPT_BUSERR, cur_vadd);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      return 0;
      return 0;
    }
    }
 
 
    if (!pending.valid && cur_area->log)
    if (!pending.valid && cur_area->log)
      fprintf (cur_area->log, "[%08x] -> read %08x\n", dataaddr, tmp);
      fprintf (cur_area->log, "[%08lx] -> read %08lx\n", dataaddr, tmp);
 
 
    return tmp;
    return tmp;
  }
  }
 
 
  /* Which set to check out? */
  /* Which set to check out? */
Line 155... Line 155...
        printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", dataaddr);
        printf("EXCEPTION: read out of memory (32-bit access to %.8lx)\n", dataaddr);
        except_handle(EXCEPT_BUSERR, cur_vadd);
        except_handle(EXCEPT_BUSERR, cur_vadd);
        return 0;
        return 0;
      }
      }
      if (!pending.valid && cur_area->log)
      if (!pending.valid && cur_area->log)
        fprintf (cur_area->log, "[%08x] -> read %08x\n", dataaddr, tmp);
        fprintf (cur_area->log, "[%08lx] -> read %08lx\n", dataaddr, tmp);
    }
    }
 
 
    dc[set].way[minway].tagaddr = tagaddr;
    dc[set].way[minway].tagaddr = tagaddr;
    for (i = 0; i < config.dc.nways; i++)
    for (i = 0; i < config.dc.nways; i++)
      if (dc[set].way[i].lru)
      if (dc[set].way[i].lru)
Line 312... Line 312...
 
 
inline void dc_clock()
inline void dc_clock()
{
{
  unsigned long addr;
  unsigned long addr;
 
 
  if (addr = mfspr(SPR_DCBPR)) {
  if ((addr = mfspr(SPR_DCBPR))) {
    dc_simulate_read(addr, 4);
    dc_simulate_read(addr, 4);
    mtspr(SPR_DCBPR, 0);
    mtspr(SPR_DCBPR, 0);
  }
  }
  if ((addr = mfspr(SPR_DCBFR)) != -1) {
  if ((addr = mfspr(SPR_DCBFR)) != -1) {
    dc_inv(addr);
    dc_inv(addr);
    mtspr(SPR_DCBFR, -1);
    mtspr(SPR_DCBFR, -1);
  }
  }
  if (addr = mfspr(SPR_DCBIR)) {
  if ((addr = mfspr(SPR_DCBIR))) {
    dc_inv(addr);
    dc_inv(addr);
    mtspr(SPR_DCBIR, 0);
    mtspr(SPR_DCBIR, 0);
  }
  }
  if (addr = mfspr(SPR_DCBWR)) {
  if ((addr = mfspr(SPR_DCBWR))) {
    mtspr(SPR_DCBWR, 0);
    mtspr(SPR_DCBWR, 0);
  }
  }
  if (addr = mfspr(SPR_DCBLR)) {
  if ((addr = mfspr(SPR_DCBLR))) {
    mtspr(SPR_DCBLR, 0);
    mtspr(SPR_DCBLR, 0);
  }
  }
}
}
 
 
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