| Line 77... |
Line 77... |
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
|
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
- refill cache line
|
- refill cache line
|
*/
|
*/
|
|
|
uint32_t dc_simulate_read(oraddr_t dataaddr, int width)
|
uint32_t dc_simulate_read(oraddr_t dataaddr, oraddr_t virt_addr, int width)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
oraddr_t tagaddr;
|
oraddr_t tagaddr;
|
uint32_t tmp;
|
uint32_t tmp;
|
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
data_ci) {
|
data_ci) {
|
if (width == 4)
|
if (width == 4)
|
tmp = evalsim_mem32(dataaddr);
|
tmp = evalsim_mem32(dataaddr, virt_addr);
|
else if (width == 2)
|
else if (width == 2)
|
tmp = evalsim_mem16(dataaddr);
|
tmp = evalsim_mem16(dataaddr, virt_addr);
|
else if (width == 1)
|
else if (width == 1)
|
tmp = evalsim_mem8(dataaddr);
|
tmp = evalsim_mem8(dataaddr, virt_addr);
|
|
|
if(!cur_area) {
|
if (cur_area && cur_area->log)
|
if (width == 4)
|
|
printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
|
dataaddr);
|
|
else if (width == 2)
|
|
printf("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
|
|
dataaddr);
|
|
else if (width == 1)
|
|
printf("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
|
|
dataaddr);
|
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
|
return 0;
|
|
} else if (cur_area->log)
|
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
|
tmp);
|
tmp);
|
|
|
return tmp;
|
return tmp;
|
}
|
}
|
| Line 158... |
Line 146... |
}
|
}
|
}
|
}
|
|
|
for (i = 0; i < (config.dc.blocksize); i += 4) {
|
for (i = 0; i < (config.dc.blocksize); i += 4) {
|
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
|
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
|
evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
|
/* FIXME: What is the virtual address meant to be? (ie. What happens if
|
|
* we read out of memory while refilling a cache line?) */
|
|
evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~ADDR_C(3)) + i) & (config.dc.blocksize - 1)), 0);
|
if(!cur_area) {
|
if(!cur_area) {
|
dc[set].way[minway].tagaddr = -1;
|
dc[set].way[minway].tagaddr = -1;
|
dc[set].way[minway].lru = 0;
|
dc[set].way[minway].lru = 0;
|
printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
|
|
dataaddr);
|
|
except_handle(EXCEPT_BUSERR, cur_vadd);
|
|
return 0;
|
return 0;
|
} else if (cur_area->log)
|
} else if (cur_area->log)
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
|
fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
|
tmp);
|
tmp);
|
}
|
}
|
| Line 203... |
Line 190... |
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- find lru way and entry and replace old tag with tag of the 'dataaddr'
|
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
|
- set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dc_simulate_write(oraddr_t dataaddr, uint32_t data, int width)
|
void dc_simulate_write(oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
|
|
int width)
|
{
|
{
|
int set, way = -1;
|
int set, way = -1;
|
int i;
|
int i;
|
oraddr_t tagaddr;
|
oraddr_t tagaddr;
|
uint32_t tmp;
|
uint32_t tmp;
|
|
|
if (width == 4)
|
if (width == 4)
|
setsim_mem32(dataaddr, data);
|
setsim_mem32(dataaddr, virt_addr, data);
|
else if (width == 2)
|
else if (width == 2)
|
setsim_mem16(dataaddr, data);
|
setsim_mem16(dataaddr, virt_addr, data);
|
else if (width == 1)
|
else if (width == 1)
|
setsim_mem8(dataaddr, data);
|
setsim_mem8(dataaddr, virt_addr, data);
|
|
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
|
data_ci ||
|
data_ci ||
|
(!cur_area))
|
(!cur_area))
|
| Line 267... |
Line 255... |
if (dc[set].way[i].lru < minlru)
|
if (dc[set].way[i].lru < minlru)
|
minway = i;
|
minway = i;
|
|
|
for (i = 0; i < (config.dc.blocksize); i += 4) {
|
for (i = 0; i < (config.dc.blocksize); i += 4) {
|
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
|
dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
|
evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
|
/* FIXME: Same comment as in dc_simulate_read */
|
|
evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)), 0);
|
if(!cur_area) {
|
if(!cur_area) {
|
dc[set].way[minway].tagaddr = -1;
|
dc[set].way[minway].tagaddr = -1;
|
dc[set].way[minway].lru = 0;
|
dc[set].way[minway].lru = 0;
|
return;
|
return;
|
}
|
}
|
