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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cache/] [dcache_model.c] - Diff between revs 1555 and 1557

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Rev 1555 Rev 1557
Line 83... Line 83...
uint32_t dc_simulate_read(oraddr_t dataaddr, oraddr_t virt_addr, int width)
uint32_t dc_simulate_read(oraddr_t dataaddr, oraddr_t virt_addr, int width)
{
{
  int set, way = -1;
  int set, way = -1;
  int i;
  int i;
  oraddr_t tagaddr;
  oraddr_t tagaddr;
  uint32_t tmp;
  uint32_t tmp = 0;
 
 
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP) ||
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE)   ||
      !(cpu_state.sprs[SPR_SR] & SPR_SR_DCE)   ||
      data_ci) {
      data_ci) {
    if (width == 4)
    if (width == 4)
Line 146... Line 146...
        minlru = dc[set].way[i].lru;
        minlru = dc[set].way[i].lru;
      }
      }
    }
    }
 
 
    for (i = 0; i < (config.dc.blocksize); i += 4) {
    for (i = 0; i < (config.dc.blocksize); i += 4) {
      dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
 
        /* FIXME: What is the virtual address meant to be? (ie. What happens if
        /* FIXME: What is the virtual address meant to be? (ie. What happens if
         * we read out of memory while refilling a cache line?) */
         * we read out of memory while refilling a cache line?) */
        evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~ADDR_C(3)) + i) & (config.dc.blocksize - 1)), 0);
      tmp = evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~ADDR_C(3)) + i) & (config.dc.blocksize - 1)), 0);
 
 
 
      dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] = tmp;
      if(!cur_area) {
      if(!cur_area) {
        dc[set].way[minway].tagaddr = -1;
        dc[set].way[minway].tagaddr = -1;
        dc[set].way[minway].lru = 0;
        dc[set].way[minway].lru = 0;
        return 0;
        return 0;
      } else if (cur_area->log)
      } else if (cur_area->log)
Line 178... Line 179...
    else if (width == 1) {
    else if (width == 1) {
      tmp = (tmp  >> (8 * (3 - (dataaddr & 3)))) & 0xff;
      tmp = (tmp  >> (8 * (3 - (dataaddr & 3)))) & 0xff;
      return tmp;
      return tmp;
    }
    }
  }
  }
 
  return 0;
}
}
 
 
/* First check if data is already in the cache and if it is:
/* First check if data is already in the cache and if it is:
    - increment DC write hit stats,
    - increment DC write hit stats,
    - set 'lru' at this way to config.dc.ustates - 1 and
    - set 'lru' at this way to config.dc.ustates - 1 and

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