| Line 35... |
Line 35... |
#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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/* Data cache */
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/* Data cache */
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extern struct dev_memarea *cur_area;
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struct dc_set {
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struct dc_set {
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struct {
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struct {
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unsigned long line[MAX_DC_BLOCK_SIZE];
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unsigned long line[MAX_DC_BLOCK_SIZE];
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unsigned long tagaddr; /* tag address */
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unsigned long tagaddr; /* tag address */
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int lru; /* least recently used */
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int lru; /* least recently used */
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| Line 75... |
Line 74... |
int i;
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int i;
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unsigned long tagaddr;
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unsigned long tagaddr;
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extern int mem_cycles;
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extern int mem_cycles;
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unsigned long tmp;
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unsigned long tmp;
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE))) {
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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data_ci) {
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if (width == 4)
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if (width == 4)
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return evalsim_mem32(dataaddr);
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return evalsim_mem32(dataaddr);
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else if (width == 2)
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else if (width == 2)
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return (unsigned long)evalsim_mem16(dataaddr);
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return (unsigned long)evalsim_mem16(dataaddr);
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else if (width == 1)
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else if (width == 1)
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| Line 127... |
Line 128... |
minway = i;
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minway = i;
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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if(!cur_area)
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if(!cur_area) {
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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return 0;
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return 0;
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}
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}
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}
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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| Line 178... |
Line 182... |
else if (width == 2)
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else if (width == 2)
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setsim_mem16(dataaddr, (unsigned short)data);
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setsim_mem16(dataaddr, (unsigned short)data);
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else if (width == 1)
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else if (width == 1)
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setsim_mem8(dataaddr, (unsigned char)data);
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setsim_mem8(dataaddr, (unsigned char)data);
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if (!cur_area)
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
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return;
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(!testsprbits(SPR_SR, SPR_SR_DCE)) ||
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data_ci ||
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if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) || (!testsprbits(SPR_SR, SPR_SR_DCE)))
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(!cur_area))
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return;
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return;
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
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| Line 229... |
Line 233... |
minway = i;
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minway = i;
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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for (i = 0; i < (config.dc.blocksize); i += 4) {
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
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if(!cur_area)
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if(!cur_area) {
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dc[set].way[minway].tagaddr = -1;
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dc[set].way[minway].lru = 0;
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return;
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return;
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}
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}
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}
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dc[set].way[minway].tagaddr = tagaddr;
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dc[set].way[minway].tagaddr = tagaddr;
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for (i = 0; i < config.dc.nways; i++)
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for (i = 0; i < config.dc.nways; i++)
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if (dc[set].way[i].lru)
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if (dc[set].way[i].lru)
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dc[set].way[i].lru--;
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dc[set].way[i].lru--;
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