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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cpu/] [or1k/] [spr_defs.h] - Diff between revs 378 and 446

Rev 378	Rev 446
Line 238...	Line 238...
`#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */`	`#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */`
`#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */`	`#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */`
`#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */`	`#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */`
`#define SPR_ITLBTR_A 0x00000010 /* Accessed */`	`#define SPR_ITLBTR_A 0x00000010 /* Accessed */`
`#define SPR_ITLBTR_D 0x00000020 /* Dirty */`	`#define SPR_ITLBTR_D 0x00000020 /* Dirty */`
`#define SPR_ITLBTR_URE 0x00000040 /* User Read Enable */`	`#define SPR_ITLBTR_SXE 0x00000040 /* Supervisor eXecute Enable */`
`#define SPR_ITLBTR_UWE 0x00000080 /* User Write Enable */`	`#define SPR_ITLBTR_UXE 0x00000080 /* User eXecute Enable */`
`#define SPR_ITLBTR_SRE 0x00000100 /* Supervisor Read Enable */`
`#define SPR_ITLBTR_SWE 0x00000200 /* Supervisor Write Enable (not used actually) */`
`#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */`	`#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */`

`/*`	`/*`
`* Bit definitions for Data Cache Control register`	`* Bit definitions for Data Cache Control register`
`*`	`*`