URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1386 and 1402

Rev 1386	Rev 1402
Line 33...	Line 33...
`#include "abstract.h"`	`#include "abstract.h"`
`#include "sprs.h"`	`#include "sprs.h"`
`#include "sim-config.h"`	`#include "sim-config.h"`
`#include "except.h"`	`#include "except.h"`
`#include "execute.h"`	`#include "execute.h"`
	`#include "dcache_model.h"`

`extern int flag;`	`extern int flag;`

`sprword sprs[MAX_SPRS];`	`sprword sprs[MAX_SPRS];`

Line 56...	Line 57...
`spr_write_ttcr (value);`	`spr_write_ttcr (value);`
`break;`	`break;`
`case SPR_TTMR:`	`case SPR_TTMR:`
`spr_write_ttmr (value);`	`spr_write_ttmr (value);`
`break;`	`break;`
	`/* Data cache simulateing stuff */`
	`case SPR_DCBPR:`
	`if(value) {`
	`dc_simulate_read(value, 4);`
	`sprs[SPR_DCBPR] = 0;`
	`}`
	`break;`
	`case SPR_DCBFR:`
	`if(value != -1) {`
	`dc_inv(value);`
	`sprs[SPR_DCBFR] = -1;`
	`}`
	`break;`
	`case SPR_DCBIR:`
	`if(value != 0) {`
	`dc_inv(value);`
	`sprs[SPR_DCBIR] = 0;`
	`}`
	`break;`
	`case SPR_DCBWR:`
	`sprs[SPR_DCBWR] = 0;`
	`break;`
	`case SPR_DCBLR:`
	`sprs[SPR_DCBLR] = 0;`
	`break;`
`case SPR_SR:`	`case SPR_SR:`
`/* Set internal flag also */`	`/* Set internal flag also */`
`if(value & SPR_SR_F) flag = 1;`	`if(value & SPR_SR_F) flag = 1;`
`else flag = 0;`	`else flag = 0;`
`sprs[regno] \|= SPR_SR_FO;`	`sprs[regno] \|= SPR_SR_FO;`