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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1402 and 1404

Rev 1402	Rev 1404
Line 34...	Line 34...
`#include "sprs.h"`	`#include "sprs.h"`
`#include "sim-config.h"`	`#include "sim-config.h"`
`#include "except.h"`	`#include "except.h"`
`#include "execute.h"`	`#include "execute.h"`
`#include "dcache_model.h"`	`#include "dcache_model.h"`
	`#include "icache_model.h"`

`extern int flag;`	`extern int flag;`

`sprword sprs[MAX_SPRS];`	`sprword sprs[MAX_SPRS];`

Line 82...	Line 83...
`sprs[SPR_DCBWR] = 0;`	`sprs[SPR_DCBWR] = 0;`
`break;`	`break;`
`case SPR_DCBLR:`	`case SPR_DCBLR:`
`sprs[SPR_DCBLR] = 0;`	`sprs[SPR_DCBLR] = 0;`
`break;`	`break;`
	`/* Instruction cache simulateing stuff */`
	`case SPR_ICBPR:`
	`if(value) {`
	`ic_simulate_fetch(value);`
	`sprs[SPR_ICBPR] = 0;`
	`}`
	`break;`
	`case SPR_ICBIR:`
	`if(value) {`
	`ic_inv(value);`
	`sprs[SPR_ICBIR] = 0;`
	`}`
	`break;`
	`case SPR_ICBLR:`
	`sprs[SPR_ICBLR] = 0;`
	`break;`
`case SPR_SR:`	`case SPR_SR:`
`/* Set internal flag also */`	`/* Set internal flag also */`
`if(value & SPR_SR_F) flag = 1;`	`if(value & SPR_SR_F) flag = 1;`
`else flag = 0;`	`else flag = 0;`
`sprs[regno] \|= SPR_SR_FO;`	`sprs[regno] \|= SPR_SR_FO;`