URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cpu/] [or1k/] [sprs.c] - Diff between revs 1551 and 1557

Rev 1551	Rev 1557
Line 37...	Line 37...
`#include "spr_defs.h"`	`#include "spr_defs.h"`
`#include "execute.h"`	`#include "execute.h"`
`#include "sprs.h"`	`#include "sprs.h"`
`#include "dcache_model.h"`	`#include "dcache_model.h"`
`#include "icache_model.h"`	`#include "icache_model.h"`
	`#include "tick.h"`
	`#include "dmmu.h"`
	`#include "immu.h"`
`#include "debug.h"`	`#include "debug.h"`

`DEFAULT_DEBUG_CHANNEL(spr);`	`DEFAULT_DEBUG_CHANNEL(spr);`
`DECLARE_DEBUG_CHANNEL(immu);`	`DECLARE_DEBUG_CHANNEL(immu);`

Line 92...	Line 95...
`break;`	`break;`
`/* Instruction cache simulateing stuff */`	`/* Instruction cache simulateing stuff */`
`case SPR_ICBPR:`	`case SPR_ICBPR:`
`/* FIXME: The arch manual does not say what happens when an invalid memory`	`/* FIXME: The arch manual does not say what happens when an invalid memory`
`* location is specified. I guess the same as for the DCBPR register */`	`* location is specified. I guess the same as for the DCBPR register */`
`ic_simulate_fetch(peek_into_itlb(value, 1), value);`	`ic_simulate_fetch(peek_into_itlb(value), value);`
`cpu_state.sprs[SPR_ICBPR] = 0;`	`cpu_state.sprs[SPR_ICBPR] = 0;`
`break;`	`break;`
`case SPR_ICBIR:`	`case SPR_ICBIR:`
`ic_inv(value);`	`ic_inv(value);`
`cpu_state.sprs[SPR_ICBIR] = 0;`	`cpu_state.sprs[SPR_ICBIR] = 0;`