| Line 38... |
Line 38... |
#include "arch.h"
|
#include "arch.h"
|
#include "branch_predict.h"
|
#include "branch_predict.h"
|
#include "abstract.h"
|
#include "abstract.h"
|
#include "labels.h"
|
#include "labels.h"
|
#include "parse.h"
|
#include "parse.h"
|
#include "execute.h"
|
|
#include "except.h"
|
#include "except.h"
|
#include "sprs.h"
|
|
#include "sim-config.h"
|
#include "sim-config.h"
|
#include "debug_unit.h"
|
#include "debug_unit.h"
|
#include "opcode/or32.h"
|
#include "opcode/or32.h"
|
|
#include "spr_defs.h"
|
|
#include "execute.h"
|
|
#include "sprs.h"
|
#include "immu.h"
|
#include "immu.h"
|
#include "dmmu.h"
|
#include "dmmu.h"
|
#include "debug.h"
|
#include "debug.h"
|
#include "stats.h"
|
#include "stats.h"
|
|
|
/* General purpose registers. */
|
/* Current cpu state */
|
uorreg_t reg[MAX_GPRS];
|
struct cpu_state cpu_state;
|
|
|
/* Instruction queue */
|
|
struct iqueue_entry iqueue[20];
|
|
|
|
/* Is current insn in execution a delay insn? */
|
|
int delay_insn;
|
|
|
|
/* Benchmark multi issue execution */
|
/* Benchmark multi issue execution */
|
int multissue[20];
|
int multissue[20];
|
int issued_per_cycle = 4;
|
int issued_per_cycle = 4;
|
|
|
/* Completition queue */
|
|
struct iqueue_entry icomplet[20];
|
|
|
|
/* Program counter (and translated PC) */
|
|
oraddr_t pc;
|
|
|
|
/* Previous program counter */
|
/* Previous program counter */
|
oraddr_t pcprev = 0;
|
oraddr_t pcprev = 0;
|
|
|
/* Temporary program counter */
|
/* Temporary program counter */
|
oraddr_t pcnext;
|
oraddr_t pcnext;
|
|
|
/* Delay instruction effective address register */
|
|
oraddr_t pcdelay;
|
|
|
|
/* CCR */
|
/* CCR */
|
int flag;
|
int flag;
|
|
|
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
|
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
|
static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;
|
static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;
|
| Line 98... |
Line 84... |
|
|
/* Local data needed for execution. */
|
/* Local data needed for execution. */
|
static int next_delay_insn;
|
static int next_delay_insn;
|
static int breakpoint;
|
static int breakpoint;
|
|
|
/* Effective address of instructions that have an effective address. This is
|
|
* only used to get dump_exe_log correct */
|
|
static oraddr_t insn_ea;
|
|
|
|
/* History of execution */
|
/* History of execution */
|
struct hist_exec *hist_exec_tail = NULL;
|
struct hist_exec *hist_exec_tail = NULL;
|
|
|
/* Implementation specific.
|
/* Implementation specific.
|
Get an actual value of a specific register. */
|
Get an actual value of a specific register. */
|
|
|
uorreg_t evalsim_reg(unsigned int regno)
|
uorreg_t evalsim_reg(unsigned int regno)
|
{
|
{
|
if (regno < MAX_GPRS) {
|
if (regno < MAX_GPRS) {
|
return reg[regno];
|
return cpu_state.reg[regno];
|
} else {
|
} else {
|
PRINTF("\nABORT: read out of registers\n");
|
PRINTF("\nABORT: read out of registers\n");
|
runtime.sim.cont_run = 0;
|
runtime.sim.cont_run = 0;
|
return 0;
|
return 0;
|
}
|
}
|
| Line 128... |
Line 111... |
{
|
{
|
if (regno == 0) /* gpr0 is always zero */
|
if (regno == 0) /* gpr0 is always zero */
|
value = 0;
|
value = 0;
|
|
|
if (regno < MAX_GPRS) {
|
if (regno < MAX_GPRS) {
|
reg[regno] = value;
|
cpu_state.reg[regno] = value;
|
} else {
|
} else {
|
PRINTF("\nABORT: write out of registers\n");
|
PRINTF("\nABORT: write out of registers\n");
|
runtime.sim.cont_run = 0;
|
runtime.sim.cont_run = 0;
|
}
|
}
|
}
|
}
|
| Line 142... |
Line 125... |
|
|
inline static void set_reg(int regno, uorreg_t value)
|
inline static void set_reg(int regno, uorreg_t value)
|
{
|
{
|
#if 0
|
#if 0
|
if (strcmp(regstr, FRAME_REG) == 0) {
|
if (strcmp(regstr, FRAME_REG) == 0) {
|
PRINTF("FP (%s) modified by insn at %x. ", FRAME_REG, pc);
|
PRINTF("FP (%s) modified by insn at %x. ", FRAME_REG, cpu_state.pc);
|
PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);
|
PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);
|
}
|
}
|
|
|
if (strcmp(regstr, STACK_REG) == 0) {
|
if (strcmp(regstr, STACK_REG) == 0) {
|
PRINTF("SP (%s) modified by insn at %x. ", STACK_REG, pc);
|
PRINTF("SP (%s) modified by insn at %x. ", STACK_REG, cpu_state.pc);
|
PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);
|
PRINTF("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);
|
}
|
}
|
#endif
|
#endif
|
|
|
if (regno < MAX_GPRS) {
|
if (regno < MAX_GPRS) {
|
reg[regno] = value;
|
cpu_state.reg[regno] = value;
|
#if RAW_RANGE_STATS
|
#if RAW_RANGE_STATS
|
raw_stats.reg[regno] = runtime.sim.cycles;
|
raw_stats.reg[regno] = runtime.sim.cycles;
|
#endif /* RAW_RANGE */
|
#endif /* RAW_RANGE */
|
} else {
|
} else {
|
PRINTF("\nABORT: write out of registers\n");
|
PRINTF("\nABORT: write out of registers\n");
|
| Line 285... |
Line 268... |
if (CHECK_BREAKPOINTS) {
|
if (CHECK_BREAKPOINTS) {
|
/* MM: Check for breakpoint. This has to be done in fetch cycle,
|
/* MM: Check for breakpoint. This has to be done in fetch cycle,
|
because of peripheria.
|
because of peripheria.
|
MM1709: if we cannot access the memory entry, we could not set the
|
MM1709: if we cannot access the memory entry, we could not set the
|
breakpoint earlier, so just check the breakpoint list. */
|
breakpoint earlier, so just check the breakpoint list. */
|
if (has_breakpoint (peek_into_itlb (pc)) && !break_just_hit) {
|
if (has_breakpoint (peek_into_itlb (cpu_state.pc)) && !break_just_hit) {
|
break_just_hit = 1;
|
break_just_hit = 1;
|
return 1; /* Breakpoint set. */
|
return 1; /* Breakpoint set. */
|
}
|
}
|
break_just_hit = 0;
|
break_just_hit = 0;
|
}
|
}
|
|
|
breakpoint = 0;
|
breakpoint = 0;
|
/* Fetch instruction. */
|
/* Fetch instruction. */
|
iqueue[0].insn_addr = pc;
|
|
iqueue[0].insn = eval_insn (pc, &breakpoint);
|
|
|
|
if (!except_pending)
|
if (!except_pending)
|
runtime.cpu.instructions++;
|
runtime.cpu.instructions++;
|
|
cpu_state.iqueue.insn_addr = cpu_state.pc;
|
|
cpu_state.iqueue.insn = eval_insn (cpu_state.pc, &breakpoint);
|
|
|
/* update_pc will be called after execution */
|
/* update_pc will be called after execution */
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* This code actually updates the PC value. */
|
/* This code actually updates the PC value. */
|
static inline void update_pc ()
|
static inline void update_pc ()
|
{
|
{
|
delay_insn = next_delay_insn;
|
cpu_state.delay_insn = next_delay_insn;
|
pcprev = pc; /* Store value for later */
|
pcprev = cpu_state.pc; /* Store value for later */
|
pc = pcnext;
|
cpu_state.pc = pcnext;
|
pcnext = delay_insn ? pcdelay : pcnext + 4;
|
pcnext = cpu_state.delay_insn ? cpu_state.pc_delay : pcnext + 4;
|
}
|
}
|
|
|
#if SIMPLE_EXECUTION
|
#if SIMPLE_EXECUTION
|
static inline
|
static inline
|
#endif
|
#endif
|
void analysis (struct iqueue_entry *current)
|
void analysis (struct iqueue_entry *current)
|
{
|
{
|
if (config.cpu.dependstats) {
|
if (config.cpu.dependstats) {
|
/* Dynamic, dependency stats. */
|
/* Dynamic, dependency stats. */
|
adddstats(icomplet[0].insn_index, current->insn_index, 1,
|
adddstats(cpu_state.icomplet.insn_index, current->insn_index, 1,
|
check_depend(icomplet, current));
|
check_depend(&cpu_state.icomplet, current));
|
|
|
/* Dynamic, functional units stats. */
|
/* Dynamic, functional units stats. */
|
addfstats(or32_opcodes[icomplet[0].insn_index].func_unit,
|
addfstats(or32_opcodes[cpu_state.icomplet.insn_index].func_unit,
|
or32_opcodes[current->insn_index].func_unit, 1,
|
or32_opcodes[current->insn_index].func_unit, 1,
|
check_depend(icomplet, current));
|
check_depend(&cpu_state.icomplet, current));
|
|
|
/* Dynamic, single stats. */
|
/* Dynamic, single stats. */
|
addsstats(current->insn_index, 1);
|
addsstats(current->insn_index, 1);
|
}
|
}
|
|
|
| Line 344... |
Line 326... |
runtime.sim.storecycles += 1;
|
runtime.sim.storecycles += 1;
|
|
|
if (or32_opcodes[current->insn_index].func_unit == it_load)
|
if (or32_opcodes[current->insn_index].func_unit == it_load)
|
runtime.sim.loadcycles += 1;
|
runtime.sim.loadcycles += 1;
|
#if 0
|
#if 0
|
if ((icomplet[0].func_unit == it_load) && check_depend())
|
if ((cpu_state.icomplet.func_unit == it_load) &&
|
|
check_depend(&cpu_state.icomplet, current))
|
runtime.sim.loadcycles++;
|
runtime.sim.loadcycles++;
|
#endif
|
#endif
|
|
|
/* Pseudo multiple issue benchmark */
|
/* Pseudo multiple issue benchmark */
|
if ((multissue[or32_opcodes[current->insn_index].func_unit] < 1) ||
|
if ((multissue[or32_opcodes[current->insn_index].func_unit] < 1) ||
|
(check_depend(icomplet, current)) || (issued_per_cycle < 1)) {
|
(check_depend(&cpu_state.icomplet, current)) || (issued_per_cycle < 1)) {
|
int i;
|
int i;
|
for (i = 0; i < 20; i++)
|
for (i = 0; i < 20; i++)
|
multissue[i] = 2;
|
multissue[i] = 2;
|
issued_per_cycle = 2;
|
issued_per_cycle = 2;
|
runtime.cpu.supercycles++;
|
runtime.cpu.supercycles++;
|
if (check_depend(icomplet, current))
|
if (check_depend(&cpu_state.icomplet, current))
|
runtime.cpu.hazardwait++;
|
runtime.cpu.hazardwait++;
|
multissue[it_unknown] = 2;
|
multissue[it_unknown] = 2;
|
multissue[it_shift] = 2;
|
multissue[it_shift] = 2;
|
multissue[it_compare] = 1;
|
multissue[it_compare] = 1;
|
multissue[it_branch] = 1;
|
multissue[it_branch] = 1;
|
| Line 377... |
Line 360... |
issued_per_cycle--;
|
issued_per_cycle--;
|
}
|
}
|
|
|
if (config.cpu.dependstats)
|
if (config.cpu.dependstats)
|
/* Instruction waits in completition buffer until retired. */
|
/* Instruction waits in completition buffer until retired. */
|
memcpy (&icomplet[0], current, sizeof (struct iqueue_entry));
|
memcpy (&cpu_state.icomplet, current, sizeof (struct iqueue_entry));
|
|
|
if (config.sim.history) {
|
if (config.sim.history) {
|
/* History of execution */
|
/* History of execution */
|
hist_exec_tail = hist_exec_tail->next;
|
hist_exec_tail = hist_exec_tail->next;
|
hist_exec_tail->addr = icomplet[0].insn_addr;
|
hist_exec_tail->addr = cpu_state.icomplet.insn_addr;
|
}
|
}
|
|
|
if (config.sim.exe_log) dump_exe_log();
|
if (config.sim.exe_log) dump_exe_log();
|
}
|
}
|
|
|
| Line 450... |
Line 433... |
}
|
}
|
|
|
/* Outputs dissasembled instruction */
|
/* Outputs dissasembled instruction */
|
void dump_exe_log ()
|
void dump_exe_log ()
|
{
|
{
|
oraddr_t insn_addr = iqueue[0].insn_addr;
|
oraddr_t insn_addr = cpu_state.iqueue.insn_addr;
|
unsigned int i, j;
|
unsigned int i, j;
|
uorreg_t operand;
|
uorreg_t operand;
|
|
|
if (insn_addr == 0xffffffff) return;
|
if (insn_addr == 0xffffffff) return;
|
if ((config.sim.exe_log_start <= runtime.cpu.instructions) &&
|
if ((config.sim.exe_log_start <= runtime.cpu.instructions) &&
|
| Line 474... |
Line 457... |
evalsim_mem8_void(insn_addr + 2),
|
evalsim_mem8_void(insn_addr + 2),
|
evalsim_mem8_void(insn_addr + 3));
|
evalsim_mem8_void(insn_addr + 3));
|
for(i = 0; i < MAX_GPRS; i++) {
|
for(i = 0; i < MAX_GPRS; i++) {
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
fprintf(runtime.sim.fexe_log, "\n");
|
fprintf(runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "GPR%2u: %"PRIxREG" ", i, reg[i]);
|
fprintf (runtime.sim.fexe_log, "GPR%2u: %"PRIxREG" ", i,
|
|
cpu_state.reg[i]);
|
}
|
}
|
fprintf (runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "\n");
|
fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
|
fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR));
|
fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
|
fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE));
|
fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
|
fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE));
|
| Line 486... |
Line 470... |
break;
|
break;
|
case EXE_LOG_SIMPLE:
|
case EXE_LOG_SIMPLE:
|
case EXE_LOG_SOFTWARE:
|
case EXE_LOG_SOFTWARE:
|
{
|
{
|
extern char *disassembled;
|
extern char *disassembled;
|
disassemble_index (iqueue[0].insn, iqueue[0].insn_index);
|
disassemble_index (cpu_state.iqueue.insn, cpu_state.iqueue.insn_index);
|
{
|
{
|
struct label_entry *entry;
|
struct label_entry *entry;
|
entry = get_label(insn_addr);
|
entry = get_label(insn_addr);
|
if (entry)
|
if (entry)
|
fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
|
fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);
|
}
|
}
|
|
|
if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
|
if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {
|
struct insn_op_struct *opd = op_start[iqueue[0].insn_index];
|
struct insn_op_struct *opd = op_start[cpu_state.iqueue.insn_index];
|
|
|
j = 0;
|
j = 0;
|
while (1) {
|
while (1) {
|
operand = eval_operand_val (iqueue[0].insn, opd);
|
operand = eval_operand_val (cpu_state.iqueue.insn, opd);
|
while (!(opd->type & OPTYPE_OP))
|
while (!(opd->type & OPTYPE_OP))
|
opd++;
|
opd++;
|
if (opd->type & OPTYPE_DIS) {
|
if (opd->type & OPTYPE_DIS) {
|
fprintf (runtime.sim.fexe_log, "EA =%"PRIxADDR" PA =%"PRIxADDR" ",
|
fprintf (runtime.sim.fexe_log, "EA =%"PRIxADDR" PA =%"PRIxADDR" ",
|
insn_ea, peek_into_dtlb(insn_ea,0,0));
|
cpu_state.insn_ea, peek_into_dtlb(cpu_state.insn_ea,0,0));
|
opd++; /* Skip of register operand */
|
opd++; /* Skip of register operand */
|
j++;
|
j++;
|
} else if ((opd->type & OPTYPE_REG) && operand) {
|
} else if ((opd->type & OPTYPE_REG) && operand) {
|
fprintf (runtime.sim.fexe_log, "r%-2i=%"PRIxREG" ",
|
fprintf (runtime.sim.fexe_log, "r%-2i=%"PRIxREG" ",
|
(int)operand, evalsim_reg (operand));
|
(int)operand, evalsim_reg (operand));
|
| Line 517... |
Line 501... |
j++;
|
j++;
|
if(opd->type & OPTYPE_LAST)
|
if(opd->type & OPTYPE_LAST)
|
break;
|
break;
|
opd++;
|
opd++;
|
}
|
}
|
if(or32_opcodes[iqueue[0].insn_index].flags & OR32_R_FLAG) {
|
if(or32_opcodes[cpu_state.iqueue.insn_index].flags & OR32_R_FLAG) {
|
fprintf (runtime.sim.fexe_log, "SR =%08x",
|
fprintf (runtime.sim.fexe_log, "SR =%08x",
|
cpu_state.sprs[SPR_SR]);
|
cpu_state.sprs[SPR_SR]);
|
j++;
|
j++;
|
}
|
}
|
while(j < 3) {
|
while(j < 3) {
|
| Line 540... |
Line 524... |
void dumpreg()
|
void dumpreg()
|
{
|
{
|
int i;
|
int i;
|
oraddr_t physical_pc;
|
oraddr_t physical_pc;
|
|
|
if ((physical_pc = peek_into_itlb(iqueue[0].insn_addr))) {
|
if ((physical_pc = peek_into_itlb(cpu_state.iqueue.insn_addr))) {
|
/*
|
/*
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", iqueue[0].insn_addr, physical_pc);
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", cpu_state.iqueue.insn_addr, physical_pc);
|
*/
|
*/
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
}
|
}
|
else {
|
else {
|
PRINTF("INTERNAL SIMULATOR ERROR:\n");
|
PRINTF("INTERNAL SIMULATOR ERROR:\n");
|
| Line 562... |
Line 546... |
PRINTF (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
|
PRINTF (" HAZARDWAIT: %u\n", runtime.cpu.hazardwait);
|
else
|
else
|
if (config.cpu.superscalar)
|
if (config.cpu.superscalar)
|
PRINTF ("\n");
|
PRINTF ("\n");
|
|
|
if ((physical_pc = peek_into_itlb(pc))) {
|
if ((physical_pc = peek_into_itlb(cpu_state.pc))) {
|
/*
|
/*
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", pc, physical_pc);
|
* PRINTF("\t\t\tEA: %08x <--> PA: %08x\n", cpu_state.pc, physical_pc);
|
*/
|
*/
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
dumpmemory(physical_pc, physical_pc + 4, 1, 0);
|
}
|
}
|
else
|
else
|
PRINTF("%"PRIxADDR": : xxxxxxxx ITLB miss follows", pc);
|
PRINTF("%"PRIxADDR": : xxxxxxxx ITLB miss follows", cpu_state.pc);
|
|
|
PRINTF(" (next insn) %s", (delay_insn?"(delay insn)":""));
|
PRINTF(" (next insn) %s", (cpu_state.delay_insn?"(delay insn)":""));
|
for(i = 0; i < MAX_GPRS; i++) {
|
for(i = 0; i < MAX_GPRS; i++) {
|
if (i % 4 == 0)
|
if (i % 4 == 0)
|
PRINTF("\n");
|
PRINTF("\n");
|
PRINTF("GPR%.2u: %"PRIxREG" ", i, evalsim_reg(i));
|
PRINTF("GPR%.2u: %"PRIxREG" ", i, evalsim_reg(i));
|
}
|
}
|
| Line 619... |
Line 603... |
runtime.cpu.instructions = 0;
|
runtime.cpu.instructions = 0;
|
runtime.cpu.supercycles = 0;
|
runtime.cpu.supercycles = 0;
|
runtime.cpu.hazardwait = 0;
|
runtime.cpu.hazardwait = 0;
|
for (i = 0; i < MAX_GPRS; i++)
|
for (i = 0; i < MAX_GPRS; i++)
|
set_reg (i, 0);
|
set_reg (i, 0);
|
memset(iqueue, 0, sizeof(iqueue));
|
memset(&cpu_state.iqueue, 0, sizeof(cpu_state.iqueue));
|
memset(icomplet, 0, sizeof(icomplet));
|
memset(&cpu_state.icomplet, 0, sizeof(cpu_state.icomplet));
|
|
|
sbuf_head = 0;
|
sbuf_head = 0;
|
sbuf_tail = 0;
|
sbuf_tail = 0;
|
sbuf_count = 0;
|
sbuf_count = 0;
|
sbuf_prev_cycles = 0;
|
sbuf_prev_cycles = 0;
|
| Line 654... |
Line 638... |
setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
|
setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
|
mtspr(SPR_SR, config.cpu.sr);
|
mtspr(SPR_SR, config.cpu.sr);
|
|
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
|
if (config.sim.verbose) PRINTF ("Starting at 0x%"PRIxADDR"\n", pcnext);
|
if (config.sim.verbose) PRINTF ("Starting at 0x%"PRIxADDR"\n", pcnext);
|
pc = pcnext;
|
cpu_state.pc = pcnext;
|
pcnext += 4;
|
pcnext += 4;
|
debug(1, "reset ...\n");
|
debug(1, "reset ...\n");
|
|
|
/* MM1409: All programs should set their stack pointer! */
|
/* MM1409: All programs should set their stack pointer! */
|
except_handle(EXCEPT_RESET, 0);
|
except_handle(EXCEPT_RESET, 0);
|
| Line 688... |
Line 672... |
update_pc();
|
update_pc();
|
except_pending = 0;
|
except_pending = 0;
|
return 0;
|
return 0;
|
}
|
}
|
|
|
decode_execute_wrapper (&iqueue[0]);
|
decode_execute_wrapper (&cpu_state.iqueue);
|
update_pc();
|
update_pc();
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* If decoding cannot be found, call this function */
|
/* If decoding cannot be found, call this function */
|
#if SIMPLE_EXECUTION
|
#if SIMPLE_EXECUTION
|
void l_invalid (struct iqueue_entry *current) {
|
void l_invalid (struct iqueue_entry *current) {
|
#else
|
#else
|
void l_invalid () {
|
void l_invalid () {
|
#endif
|
#endif
|
except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
|
except_handle(EXCEPT_ILLEGAL, cpu_state.iqueue.insn_addr);
|
}
|
}
|
|
|
#if !SIMPLE_EXECUTION
|
#if !SIMPLE_EXECUTION
|
|
|
/* Include decode_execute function */
|
/* Include decode_execute function */
|
| Line 723... |
Line 707... |
#if RAW_RANGE_STATS
|
#if RAW_RANGE_STATS
|
int delta = (runtime.sim.cycles - raw_stats.reg[regno]);
|
int delta = (runtime.sim.cycles - raw_stats.reg[regno]);
|
if ((unsigned long)delta < (unsigned long)MAX_RAW_RANGE)
|
if ((unsigned long)delta < (unsigned long)MAX_RAW_RANGE)
|
raw_stats.range[delta]++;
|
raw_stats.range[delta]++;
|
#endif /* RAW_RANGE */
|
#endif /* RAW_RANGE */
|
return reg[regno];
|
return cpu_state.reg[regno];
|
} else {
|
} else {
|
PRINTF("\nABORT: read out of registers\n");
|
PRINTF("\nABORT: read out of registers\n");
|
runtime.sim.cont_run = 0;
|
runtime.sim.cont_run = 0;
|
return 0;
|
return 0;
|
}
|
}
|
| Line 755... |
Line 739... |
ret = eval_operand_val (insn, opd);
|
ret = eval_operand_val (insn, opd);
|
while (!(opd->type & OPTYPE_OP))
|
while (!(opd->type & OPTYPE_OP))
|
opd++;
|
opd++;
|
opd++;
|
opd++;
|
ret += eval_reg (eval_operand_val (insn, opd));
|
ret += eval_reg (eval_operand_val (insn, opd));
|
insn_ea = ret;
|
cpu_state.insn_ea = ret;
|
return ret;
|
return ret;
|
}
|
}
|
if (opd->type & OPTYPE_REG)
|
if (opd->type & OPTYPE_REG)
|
return eval_reg (eval_operand_val (insn, opd));
|
return eval_reg (eval_operand_val (insn, opd));
|
|
|
| Line 801... |
Line 785... |
if (insn_index < 0)
|
if (insn_index < 0)
|
l_invalid(current);
|
l_invalid(current);
|
else {
|
else {
|
or32_opcodes[insn_index].exec(current);
|
or32_opcodes[insn_index].exec(current);
|
}
|
}
|
if (do_stats) analysis(&iqueue[0]);
|
|
|
if (do_stats) analysis(&cpu_state.iqueue);
|
}
|
}
|
|
|
#define SET_PARAM0(val) set_operand(0, val, current->insn_index, current->insn)
|
#define SET_PARAM0(val) set_operand(0, val, current->insn_index, current->insn)
|
|
|
#define PARAM0 eval_operand(0, current->insn_index, current->insn)
|
#define PARAM0 eval_operand(0, current->insn_index, current->insn)
|
