| Line 255... |
Line 255... |
}
|
}
|
|
|
/* Sets a new SPR_SR_OV value, based on next register value */
|
/* Sets a new SPR_SR_OV value, based on next register value */
|
|
|
#if SET_OV_FLAG
|
#if SET_OV_FLAG
|
#define set_ov_flag(value) if((value) & 0x80000000) setsprbits (SPR_SR, SPR_SR_OV, 1); else setsprbits (SPR_SR, SPR_SR_OV, 0)
|
#define set_ov_flag(value) \
|
|
if((value) & 0x80000000) \
|
|
cpu_state.sprs[SPR_SR] |= SPR_SR_OV; \
|
|
else \
|
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV
|
#else
|
#else
|
#define set_ov_flag(value)
|
#define set_ov_flag(value)
|
#endif
|
#endif
|
|
|
/* Modified by CZ 26/05/01 for new mode execution */
|
/* Modified by CZ 26/05/01 for new mode execution */
|
/* Fetch returns nonzero if instruction should NOT be executed. */
|
/* Fetch returns nonzero if instruction should NOT be executed. */
|
static inline int fetch()
|
static inline int fetch(void)
|
{
|
{
|
static int break_just_hit = 0;
|
static int break_just_hit = 0;
|
|
|
if (CHECK_BREAKPOINTS) {
|
if (CHECK_BREAKPOINTS) {
|
/* MM: Check for breakpoint. This has to be done in fetch cycle,
|
/* MM: Check for breakpoint. This has to be done in fetch cycle,
|
| Line 588... |
Line 592... |
decode_execute (current);
|
decode_execute (current);
|
#endif
|
#endif
|
|
|
#if SET_OV_FLAG
|
#if SET_OV_FLAG
|
/* Check for range exception */
|
/* Check for range exception */
|
if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))
|
if((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) &&
|
|
(cpu_state.sprs[SPR_SR] & SPR_SR_OV))
|
except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
|
except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
|
#endif
|
#endif
|
|
|
if(breakpoint)
|
if(breakpoint)
|
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
|
except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
|
| Line 640... |
Line 645... |
hist_exec_tail->next = hist_exec_head;
|
hist_exec_tail->next = hist_exec_head;
|
hist_exec_head->prev = hist_exec_tail;
|
hist_exec_head->prev = hist_exec_tail;
|
|
|
/* Cpu configuration */
|
/* Cpu configuration */
|
cpu_state.sprs[SPR_UPR] = config.cpu.upr;
|
cpu_state.sprs[SPR_UPR] = config.cpu.upr;
|
setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);
|
cpu_state.sprs[SPR_VR] = config.cpu.rev & SPR_VR_REV;
|
setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
|
cpu_state.sprs[SPR_VR] |= config.cpu.ver << 16;
|
cpu_state.sprs[SPR_SR] = config.cpu.sr;
|
cpu_state.sprs[SPR_SR] = config.cpu.sr;
|
|
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */
|
if (config.sim.verbose) PRINTF ("Starting at 0x%"PRIxADDR"\n", pcnext);
|
if (config.sim.verbose) PRINTF ("Starting at 0x%"PRIxADDR"\n", pcnext);
|
cpu_state.pc = pcnext;
|
cpu_state.pc = pcnext;
|
