| Line 230... |
Line 230... |
GEN ("/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
|
GEN ("/* %s -- generated by OpenRISC Custom Unit Compiler\n", tmp);
|
GEN (" (C) 2002 OpenCores http://www.opencores.org/\n");
|
GEN (" (C) 2002 OpenCores http://www.opencores.org/\n");
|
GEN (" function \"%s\"\n", funcname);
|
GEN (" function \"%s\"\n", funcname);
|
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
|
GEN (" at %08x - %08x\n", f->start_addr, f->end_addr);
|
GEN (" num BBs %i */\n\n", f->num_bb);
|
GEN (" num BBs %i */\n\n", f->num_bb);
|
|
|
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
|
GEN (" swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
|
GEN (" swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
|
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i,\n");
|
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i,\n");
|
| Line 680... |
Line 682... |
|
|
GEN ("\n/* Basic blocks state machine */\n");
|
GEN ("\n/* Basic blocks state machine */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" else if (end_o) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
GEN (" else if (end_o) begin\n");
|
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
|
for (i = 0; i < f->num_bb; i++) {
|
for (i = 0; i < f->num_bb; i++) {
|
GEN (" end else if (bb_start[%i]) begin\n", i);
|
GEN (" end else if (bb_start[%i]) begin\n", i);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
|
GEN (" bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
|
}
|
}
|
GEN (" end else if (end_o) begin\n");
|
GEN (" end else if (end_o) begin\n");
|
| Line 702... |
Line 705... |
{
|
{
|
FILE *fo;
|
FILE *fo;
|
int i, j, nrf, first;
|
int i, j, nrf, first;
|
char tmp[256];
|
char tmp[256];
|
int ncallees[MAX_FUNCS];
|
int ncallees[MAX_FUNCS];
|
|
int nl[MAX_FUNCS], ns[MAX_FUNCS];
|
int maxncallees = 0;
|
int maxncallees = 0;
|
sprintf (tmp, "%s.v", filename);
|
sprintf (tmp, "%s.v", filename);
|
|
|
for (i = 0, nrf = 0; i < nfuncs; i++) {
|
for (i = 0, nrf = 0; i < nfuncs; i++) {
|
if (f[i]) f[i]->tmp = nrf++;
|
nl[i] = ns[i] = 0;
|
ncallees[i] = 0;
|
ncallees[i] = 0;
|
}
|
if (f[i]) {
|
if (!nrf) return;
|
f[i]->tmp = nrf++;
|
|
for (j = 0; j < f[i]->nmsched; j++)
|
for (i = 0; i < nfuncs; i++) if (f[i])
|
if (f[i]->mtype[j] & MT_LOAD) nl[i]++;
|
|
else if (f[i]->mtype[j] & MT_STORE) ns[i]++;
|
for (j = 0; j < f[i]->nfdeps; j++)
|
for (j = 0; j < f[i]->nfdeps; j++)
|
ncallees[f[i]->fdeps[j]->tmp]++;
|
ncallees[f[i]->fdeps[j]->tmp]++;
|
|
}
|
|
}
|
|
if (!nrf) return;
|
|
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
|
if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
|
|
|
log ("Generating verilog file \"%s\"\n", tmp);
|
log ("Generating verilog file \"%s\"\n", tmp);
|
| Line 736... |
Line 744... |
GEN (" */\n\n");
|
GEN (" */\n\n");
|
|
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("`include \"timescale.v\"\n\n");
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN ("module %s (clk, rst,\n", filename);
|
GEN (" /* Load and store master Wishbone ports */\n");
|
GEN (" /* Load and store master Wishbone ports */\n");
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cycstb_o,\n");
|
GEN (" lwb_adr_o, lwb_dat_i, lwb_cyc_o, lwb_stb_o,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i,\n");
|
GEN (" lwb_sel_o, lwb_linbrst_o, lwb_ack_i, lwb_we_o,\n");
|
GEN (" swb_adr_o, swb_dat_o, swb_cycstb_o,\n");
|
GEN (" swb_adr_o, swb_dat_o, swb_cyc_o, swb_stb_o,\n");
|
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i,\n\n");
|
GEN (" swb_sel_o, swb_linbrst_o, swb_ack_i, swb_we_o,\n\n");
|
GEN (" /* cuc interface */\n");
|
GEN (" /* cuc interface */\n");
|
GEN (" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_ack_o);\n\n");
|
GEN (" cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_ack_o);\n\n");
|
|
|
GEN ("parameter Tp = 1;\n");
|
GEN ("parameter Tp = 1;\n");
|
GEN ("\n/* module ports */\n");
|
GEN ("\n/* module ports */\n");
|
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
|
GEN ("input clk, rst, cuc_stb_i, cuc_we_i;\n");
|
GEN ("input lwb_ack_i, swb_ack_i, lwb_linbrst_o, swb_linbrst_o;\n");
|
GEN ("input lwb_ack_i, swb_ack_i;\n");
|
GEN ("output lwb_cycstb_o, lwb_linbrst_o;\n");
|
GEN ("output lwb_cyc_o, lwb_stb_o, lwb_we_o, lwb_linbrst_o;\n");
|
GEN ("output swb_cycstb_o swb_linbrst_o;\n");
|
GEN ("reg lwb_cyc_o, lwb_stb_o, lwb_we_o, lwb_linbrst_o;\n");
|
GEN ("output cuc_ack_o;\n");
|
GEN ("output swb_cyc_o, swb_stb_o, swb_we_o, swb_linbrst_o;\n");
|
|
GEN ("reg swb_cyc_o, swb_stb_o, swb_we_o, swb_linbrst_o;\n");
|
|
GEN ("output cuc_ack_o; /* Not registered ! */\n");
|
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("output [3:0] lwb_sel_o, swb_sel_o;\n");
|
|
GEN ("reg [3:0] lwb_sel_o, swb_sel_o;\n");
|
GEN ("output [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
GEN ("output [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
|
GEN ("reg [31:0] lwb_adr_o, swb_adr_o, swb_dat_o, cuc_dat_o;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [15:0] cuc_adr_i;\n");
|
GEN ("input [31:0] lwb_dat_i, cuc_dat_i;\n\n");
|
GEN ("input [31:0] lwb_dat_i, cuc_dat_i;\n\n");
|
|
|
GEN ("wire [%2i:0] i_we, i_re, i_start, i_finish, i_selected, i_first_reg;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_bidok, main_start, main_end;\n", nrf - 1);
|
GEN ("wire [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
|
|
GEN ("wire [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
|
|
GEN ("wire [%2i:0] i_lwb_cycstb, i_swb_cycstb;\n", nrf - 1);
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
GEN ("reg [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
|
|
|
GEN ("assign i_selected = {\n");
|
GEN ("assign i_selected = {\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
GEN (" cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
|
| Line 776... |
Line 790... |
|
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_ack_o}};\n", nrf);
|
GEN ("assign i_start = i_go_bsy & {%i{cuc_ack_o}};\n", nrf);
|
GEN ("assign i_start_bidok = {\n");
|
GEN ("assign i_start_bidok = {\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++)
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
GEN (" i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
|
GEN ("assign main_start = start_i & i_selected & i_first_reg & i_we;\n");
|
GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
|
GEN ("assign main_end = {%i{end_i}} & i_selected;\n");
|
GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
|
|
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
|
GEN (" if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
|
GEN (" else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
|
GEN (" else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
|
|
|
|
/* Function specific data */
|
/* Function specific data */
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
int ci = 0, co = 0;
|
int ci = 0, co = 0;
|
int fn = f[i]->tmp;
|
int fn = f[i]->tmp;
|
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
|
GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
|
| Line 799... |
Line 814... |
}
|
}
|
if (ci) GEN (";\n");
|
if (ci) GEN (";\n");
|
|
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
|
GEN ("%s i%i_r%io", first ? "/* outputs */\nreg [31:0]" : ",", fn, j);
|
GEN ("%s i%i_r%io", first ? "/* outputs */\nwire [31:0]" : ",", fn, j);
|
first = 0;
|
first = 0;
|
co++;
|
co++;
|
}
|
}
|
if (co) GEN (";\n");
|
if (co) GEN (";\n");
|
|
GEN ("wire [31:0] i%i_lwb_adr, i%i_swb_adr;\n", fn, fn);
|
|
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
GEN (" if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
|
GEN (" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
GEN (" else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
|
|
|
| Line 815... |
Line 831... |
GEN ("\n/* write register access */\n");
|
GEN ("\n/* write register access */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("begin\n");
|
GEN ("begin\n");
|
GEN (" if (rst) begin\n");
|
GEN (" if (rst) begin\n");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (" i%i_r%-2i <= #Tp 32'h0;\n", fn, j);
|
GEN (" i%i_r%ii <= #Tp 32'h0;\n", fn, j);
|
GEN (" end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
|
GEN (" end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
|
GEN (" case (cuc_adr_i[5:0])\n");
|
GEN (" case (cuc_adr_i[5:0])\n");
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (" %-2i: r%i <= #Tp cuc_dat_i;\n", j, j);
|
GEN (" %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
|
GEN (" endcase\n");
|
GEN (" endcase\n");
|
GEN ("end\n");
|
GEN ("end\n");
|
}
|
}
|
|
|
GEN ("\n");
|
GEN ("\n");
|
| Line 842... |
Line 858... |
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
co = 0;
|
co = 0;
|
for (j = 0; j < MAX_REGS; j++)
|
for (j = 0; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
|
|
|
GEN ("if (cuc_addr_i[15:6] == %i)", f[i]->tmp);
|
GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
|
if (co) {
|
if (co) {
|
first = 1;
|
first = 1;
|
GEN ("\n case (cuc_adr_i[5:0])\n");
|
GEN ("\n case (cuc_adr_i[5:0])\n");
|
for (j = 0; j < MAX_REGS; j++)
|
for (j = 0; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%i;\n", j, f[i]->tmp, j);
|
GEN (" %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j, f[i]->tmp, j);
|
GEN (" endcase\n");
|
GEN (" endcase\n");
|
} else {
|
} else {
|
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" cuc_dat_o <= #Tp 32'hx;\n");
|
}
|
}
|
GEN (" else ");
|
GEN (" else ");
|
}
|
}
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN ("cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" else cuc_dat_o <= #Tp 32'hx;\n");
|
GEN (" end else cuc_dat_o <= #Tp 32'hx;\n");
|
GEN ("end\n");
|
|
|
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("\n/* read register access - acknowledge */\n");
|
GEN ("always @(cuc_stb_i or cuc_we_i or cuc_adr_i");
|
GEN ("assign cuc_ack_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
|
for (i = 0; i < nrf; i++) GEN (" or main_end%i", i);
|
|
GEN (")\n");
|
|
GEN (" if (cuc_stb_i && cuc_we_i) cuc_ack_o <= #Tp |(i_selected & main_end)\n");
|
|
GEN (" else cuc_ack_o <= #Tp 1'b0;\n");
|
|
GEN ("end\n");
|
|
}
|
}
|
|
|
for (j = 0; j < 2; j++) {
|
for (j = 0; j < 2; j++) {
|
char t = j ? 's' : 'l';
|
char t = j ? 's' : 'l';
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
|
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_sel;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
GEN ("reg [%i:0] %cm_bid;\n", log2 (nrf), t);
|
|
GEN ("reg %ccyc_ip;\n\n", t);
|
|
GEN ("always @(posedge clk)\n");
|
|
GEN ("begin\n");
|
|
GEN (" %cwb_we_o <= #Tp 1'b%i;\n", t, j);
|
|
GEN (" %cwb_cyc_o <= #Tp |i_%cwb_cycstb;\n", t, t);
|
|
GEN (" %cwb_stb_o <= #Tp |i_%cwb_cycstb;\n", t, t);
|
|
GEN ("end\n");
|
|
|
GEN ("\n/* highest bid */\n");
|
GEN ("\n/* highest bid */\n");
|
GEN ("always @(");
|
GEN ("always @(");
|
for (i = 0; i < nrf; i++) GEN ("%si%i_%cwb_cycstb", i > 0 ? " or " : "", i, t);
|
for (i = 0; i < nrf; i++) GEN ("%si_%cwb_cycstb", i > 0 ? " or " : "", t);
|
GEN (")\n");
|
GEN (")\n");
|
for (i = 0; i < nrf; i++) GEN (" %sif (i%i_%cwb_cycstb) %cm_bid <= %i'h%x;\n",
|
for (i = 0; i < nrf; i++) GEN (" %sif (i_%cwb_cycstb) %cm_bid = %i'h%x;\n",
|
i ? "else " : "", i, t, t, log2 (nrf) + 1, i);
|
i ? "else " : "", t, t, log2 (nrf) + 1, i);
|
|
|
GEN ("\n/* selected transfer */\n");
|
GEN ("\n/* selected transfer */\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN ("always @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) %cm_sel <= #Tp %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
|
GEN (" if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2 (nrf) + 1);
|
GEN (" else if (%cwb_ack_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
|
GEN (" else if (%cwb_ack_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2 (nrf) + 1);
|
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
|
GEN (" else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
|
|
|
GEN ("\n/* Cycle */\n");
|
GEN ("\n/* Cycle */\n");
|
GEN ("assign %cwb_cyc_o = (lwb_cycstb | swb_cycstb);\n", t);
|
|
GEN ("assign %cwb_stb_o = %cwb_stb_o;\n", t, t);
|
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN ("\nalways @(posedge clk or posedge rst)\n");
|
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
|
GEN (" if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
|
GEN (" else if (%cwb_ack_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
|
GEN (" else if (%cwb_ack_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
|
GEN (" else %ccyc_ip <= #Tp %cwb_cyc_o;\n", t, t);
|
GEN (" else %ccyc_ip <= #Tp %cwb_cyc_o;\n", t, t);
|
}
|
}
|
|
|
GEN ("\n/* Acknowledge */\n");
|
GEN ("\n/* Acknowledge */\n");
|
for (i = 0; i < nrf; i++)
|
for (i = 0; i < nrf; i++) {
|
GEN ("assign i%i_swb_ack = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & swb_ack_i;\n", i, i, i);
|
GEN ("wire i%i_swb_ack = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & swb_ack_i;\n", i, i, i);
|
|
GEN ("wire i%i_lwb_ack = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & lwb_ack_i;\n", i, i, i);
|
|
}
|
|
|
GEN ("\n/* Data */\n");
|
GEN ("\n/* data, address selects and burst enables */\n");
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for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_swb_dat;\n", i);
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for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_swb_dat;\n", i);
|
GEN ("\nassign swb_dat_o = ");
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for (i = 0; i < nrf; i++) GEN ("wire i%i_swb_linbrst, i%i_lwb_linbrst;\n", i, i);
|
|
for (i = 0; i < nrf; i++) GEN ("wire [3:0] i%i_swb_sel, i%i_lwb_sel;\n", i, i);
|
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_lwb_dat = lwb_dat_i;\n", i);
|
|
GEN ("\nalways @(posedge clk)\n");
|
|
GEN ("begin\n");
|
|
GEN (" swb_dat_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_swb_dat : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_swb_dat : ", i, i);
|
GEN ("i%i_swb_dat;\n\n", nrf - 1);
|
GEN ("i%i_swb_dat;\n", nrf - 1);
|
|
GEN (" swb_adr_o <= #Tp ");
|
for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_lwb_dat = lwb_dat_i;\n", i);
|
for (i = 0; i < nrf - 1; i++)
|
|
GEN ("\n sm_bid == %i ? i%i_swb_adr : ", i, i);
|
GEN ("\n/* selects */\n");
|
GEN ("i%i_swb_adr;\n", nrf - 1);
|
for (i = 0; i < nrf; i++) GEN ("wire [3:0] i%i_swb_sel, i%i_lwb_sel;\n", i, i);
|
GEN (" swb_sel_o <= #Tp ");
|
GEN ("\nassign swb_sel_o = ");
|
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n sm_bid == %i ? i%i_swb_sel : ", i, i);
|
GEN ("\n sm_bid == %i ? i%i_swb_sel : ", i, i);
|
GEN ("i%i_swb_sel;\n", nrf - 1);
|
GEN ("i%i_swb_sel;\n", nrf - 1);
|
GEN ("\nassign lwb_sel_o = ");
|
GEN (" swb_linbrst_o <= #Tp ");
|
|
for (i = 0; i < nrf - 1; i++)
|
|
GEN ("\n sm_bid == %i ? i%i_swb_linbrst : ", i, i);
|
|
GEN ("i%i_swb_linbrst;\n", nrf - 1);
|
|
GEN ("end\n\n");
|
|
|
|
GEN ("always @(posedge clk)\n");
|
|
GEN ("begin\n");
|
|
GEN (" lwb_adr_o <= #Tp ");
|
|
for (i = 0; i < nrf - 1; i++)
|
|
GEN ("\n lm_bid == %i ? i%i_lwb_adr : ", i, i);
|
|
GEN ("i%i_lwb_adr;\n", nrf - 1);
|
|
GEN (" lwb_sel_o <= #Tp ");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf - 1; i++)
|
GEN ("\n lm_bid == %i ? i%i_lwb_sel : ", i, i);
|
GEN ("\n lm_bid == %i ? i%i_lwb_sel : ", i, i);
|
GEN ("i%i_lwb_sel;\n", nrf - 1);
|
GEN ("i%i_lwb_sel;\n", nrf - 1);
|
|
GEN (" lwb_linbrst_o <= #Tp ");
|
GEN ("\n/* write enable */\n");
|
for (i = 0; i < nrf - 1; i++)
|
for (i = 0; i < nrf; i++) GEN ("wire i%i_swb_we, i%i_lwb_we;\n", i, i);
|
GEN ("\n lm_bid == %i ? i%i_lwb_linbrst : ", i, i);
|
GEN ("\nassign swb_we_o = ");
|
|
for (i = 0; i < nrf - 1; i++) GEN ("\n sm_bid == %i ? i%i_swb_we : ", i, i);
|
|
GEN ("i%i_swb_we;\n", nrf - 1);
|
|
|
|
GEN ("\nassign lwb_we_o = ");
|
|
for (i = 0; i < nrf - 1; i++) GEN ("\n lm_bid == %i ? i%i_lwb_we : ", i, i);
|
|
GEN ("i%i_lwb_we;\n", nrf - 1);
|
|
|
|
GEN ("\n/* burst enable */\n");
|
|
for (i = 0; i < nrf; i++) GEN ("wire i%i_swb_linbrst, i%i_lwb_linbrst;\n", i, i);
|
|
GEN ("\nassign swb_linbrst_o = ");
|
|
for (i = 0; i < nrf - 1; i++) GEN ("\n sm_bid == %i ? i%i_swb_linbrst : ", i, i);
|
|
GEN ("i%i_swb_linbrst;\n", nrf - 1);
|
|
GEN ("\n\nassign lwb_linbrst_o = ");
|
|
for (i = 0; i < nrf - 1; i++) GEN ("\n lm_bid == %i ? i%i_lwb_linbrst : ", i, i);
|
|
GEN ("i%i_lwb_linbrst;\n", nrf - 1);
|
GEN ("i%i_lwb_linbrst;\n", nrf - 1);
|
|
GEN ("end\n\n");
|
|
|
/* start/end signals */
|
/* start/end signals */
|
GEN ("\n\n/* start/end signals */\n");
|
GEN ("\n\n/* start/end signals */\n");
|
|
|
for (i = 0; i < nrf; i++) {
|
for (i = 0; i < nrf; i++) {
|
if (log2 (maxncallees + 1))
|
if (log2 (maxncallees + 1))
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
|
log2 (maxncallees + 1), i, i, i, i, i);
|
log2 (maxncallees + 1), i, i, i, i, i);
|
else GEN ("wire i%i_current = 0;\n", i);
|
else GEN ("wire i%i_current = 0;\n", i);
|
}
|
}
|
GEN ("\n");
|
GEN ("\n");
|
|
|
for (i = 0, first = 1; i < nrf; i++) {
|
|
GEN ("%si%i_current == %i && i_end[%i]", first ? "assign end_o = " : "\n || ", i, ncallees[i], i);
|
|
first = 0;
|
|
}
|
|
GEN (";\n\n");
|
|
|
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
|
if (log2 (ncallees[i])) {
|
if (log2 (ncallees[i])) {
|
GEN ("reg [%i:0] i%i_start_bid;\n", log2 (ncallees[i]), j);
|
GEN ("reg [%i:0] i%i_start_bid;\n", log2 (ncallees[i]), j);
|
GEN ("always @(start%i", f[i]->tmp);
|
GEN ("always @(start%i", f[i]->tmp);
|
for (j = 0, first = 1; j < f[i]->nfdeps; j++)
|
for (j = 0, first = 1; j < f[i]->nfdeps; j++)
|
| Line 974... |
Line 986... |
}
|
}
|
GEN ("\n");
|
GEN ("\n");
|
|
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
for (i = 0; i < nfuncs; i++) if (f[i]) {
|
int nf = f[i]->tmp;
|
int nf = f[i]->tmp;
|
GEN ("\n%s i%i(.clk(clk), .rst(rst),\n", prof_func[i].name, nf);
|
GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
|
GEN ("");
|
GEN ("");
|
GEN (" .lwb_adr_o(i%i_lwb_adr), .lwb_dat_i(i%i_lwb_dat), .lwb_cycstb_o(i%i_lwb_cycstb),\n",
|
GEN (" .lwb_adr_o(i%i_lwb_adr), .lwb_dat_i(i%i_lwb_dat), .lwb_cycstb_o(i_lwb_cycstb[%i]),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .lwb_sel_o(i%i_lwb_sel), .lwb_linbrst_o(i%i_lwb_linbrst), .lwb_ack_i(i%i_lwb_ack),\n",
|
GEN (" .lwb_sel_o(i%i_lwb_sel), .lwb_linbrst_o(i%i_lwb_linbrst), .lwb_ack_i(i%i_lwb_ack),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .swb_adr_o(i%i_swb_adr), .swb_dat_o(i%i_swb_dat), .swb_cycstb_o(i%i_swb_cycstb),\n",
|
GEN (" .swb_adr_o(i%i_swb_adr), .swb_dat_o(i%i_swb_dat), .swb_cycstb_o(i_swb_cycstb[%i]),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" .swb_sel_o(i%i_swb_sel), .swb_linbrst_o(i%i_swb_linbrst), .swb_ack_i(i%i_swb_ack),\n",
|
GEN (" .swb_sel_o(i%i_swb_sel), .swb_linbrst_o(i%i_swb_linbrst), .swb_ack_i(i%i_swb_ack),\n",
|
nf, nf, nf);
|
nf, nf, nf);
|
GEN (" ");
|
GEN (" ");
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
|
GEN (".r%i_i(i_r%ii[%i]), ", j, j, nf), first = 0;
|
GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
|
|
|
if (first) GEN ("\n ");
|
if (first) GEN ("\n ");
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
for (j = 0, first = 1; j < MAX_REGS; j++)
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
|
GEN (".r%i_o(i_r%io[%i]), ", j, j, nf), first = 0;
|
GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
|
if (first) GEN ("\n ");
|
if (first) GEN ("\n ");
|
if (f[i]->nfdeps) {
|
if (f[i]->nfdeps) {
|
GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
|
GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
|
GEN (" .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
|
GEN (" .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
|
GEN (" .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n ");
|
GEN (" .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n ");
|
