URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [debug/] [debug_unit.c] - Diff between revs 1358 and 1359

Rev 1358	Rev 1359
Line 397...	Line 397...

`if(!verify_memoryarea(address))`	`if(!verify_memoryarea(address))`
`err = JTAG_PROXY_INVALID_ADDRESS;`	`err = JTAG_PROXY_INVALID_ADDRESS;`
`else {`	`else {`
`// circumvent the read-only check usually done for mem accesses`	`// circumvent the read-only check usually done for mem accesses`
`// data is in host order, because that's what simmem_write_word needs`	`// data is in host order, because that's what set_direct32 needs`
`simmem_write_word(address, data);`	`set_direct32(address, data, NULL, 0, 0);`
`}`	`}`
`return err;`	`return err;`
`}`	`}`

`/* Reads from bus address */`	`/* Reads from bus address */`
Line 411...	Line 411...
`int err = 0;`	`int err = 0;`
`if(!verify_memoryarea(address))`	`if(!verify_memoryarea(address))`
`err = JTAG_PROXY_INVALID_ADDRESS;`	`err = JTAG_PROXY_INVALID_ADDRESS;`
`else`	`else`
`{`	`{`
`*data=simmem_read_word(address);`	`*data=eval_direct32(address, NULL, 0, 0);`
`}`	`}`
`debug (2, "MEMREAD (%08x) = %08lx\n", address, *data);`	`debug (2, "MEMREAD (%08x) = %08lx\n", address, *data);`
`return err;`	`return err;`
`}`	`}`