| Line 375... |
Line 375... |
/* Called when all the bits have been shifted out of the shift register */
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/* Called when all the bits have been shifted out of the shift register */
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void uart_char_clock(void *dat)
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void uart_char_clock(void *dat)
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{
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{
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struct dev_16450 *uart = dat;
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struct dev_16450 *uart = dat;
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TRACE("Sending data in shift reg: 0x%02lx\n", uart->iregs.txser);
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TRACE("Sending data in shift reg: 0x%02"PRIx8"\n", uart->iregs.txser);
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/* We've sent all bits */
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/* We've sent all bits */
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send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
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send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
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if(!uart->istat.txbuf_full)
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if(!uart->istat.txbuf_full)
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uart->regs.lsr |= UART_LSR_TXSERE;
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uart->regs.lsr |= UART_LSR_TXSERE;
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| Line 417... |
Line 417... |
uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
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uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
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uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
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uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
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uart->istat.txbuf_full--;
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uart->istat.txbuf_full--;
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uart->regs.lsr &= ~UART_LSR_TXSERE;
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uart->regs.lsr &= ~UART_LSR_TXSERE;
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TRACE("Moveing head of TX fifo (fill: %i) to shift reg 0x%02lx\n",
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TRACE("Moveing head of TX fifo (fill: %i) to shift reg 0x%02"PRIx8"\n",
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uart->istat.txbuf_full, uart->iregs.txser);
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uart->istat.txbuf_full, uart->iregs.txser);
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/* Schedules a char_clock to run in the correct amount of time */
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/* Schedules a char_clock to run in the correct amount of time */
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if(!(uart->regs.lcr & UART_LCR_SBC)) {
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if(!(uart->regs.lcr & UART_LCR_SBC)) {
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SCHED_ADD(uart_char_clock, uart, uart->char_clks * UART_CLOCK_DIVIDER);
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SCHED_ADD(uart_char_clock, uart, uart->char_clks * UART_CLOCK_DIVIDER);
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| Line 933... |
Line 933... |
PRINTF("LCR : %.2x MCR : %.2x\n", uart->regs.lcr, uart->regs.mcr);
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PRINTF("LCR : %.2x MCR : %.2x\n", uart->regs.lcr, uart->regs.mcr);
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PRINTF("LSR : %.2x MSR : %.2x\n", uart->regs.lsr, uart->regs.msr);
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PRINTF("LSR : %.2x MSR : %.2x\n", uart->regs.lsr, uart->regs.msr);
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PRINTF("SCR : %.2x\n", uart->regs.scr);
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PRINTF("SCR : %.2x\n", uart->regs.scr);
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PRINTF("\nInternal registers (sim debug):\n");
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PRINTF("\nInternal registers (sim debug):\n");
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PRINTF("RXSER: %.2lx TXSER: %.2lx\n", uart->iregs.rxser, uart->iregs.txser);
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PRINTF("RXSER: %.2"PRIx16" TXSER: %.2"PRIx8"\n", uart->iregs.rxser,
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uart->iregs.txser);
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PRINTF("\nInternal status (sim debug):\n");
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PRINTF("\nInternal status (sim debug):\n");
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PRINTF("char_clks: %ld\n", uart->char_clks);
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PRINTF("char_clks: %ld\n", uart->char_clks);
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PRINTF("rxbuf_full: %d txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
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PRINTF("rxbuf_full: %d txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
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PRINTF("Using IRQ%i\n", uart->irq);
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PRINTF("Using IRQ%i\n", uart->irq);
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