Line 646... |
Line 646... |
Read a register
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Read a register
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*/
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*/
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uint32_t eth_read32( oraddr_t addr, void *dat )
|
uint32_t eth_read32( oraddr_t addr, void *dat )
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{
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{
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struct eth_device *eth = dat;
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struct eth_device *eth = dat;
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addr -= eth->baseaddr;
|
|
|
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switch( addr ) {
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switch( addr ) {
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case ETH_MODER: return eth->regs.moder;
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case ETH_MODER: return eth->regs.moder;
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case ETH_INT_SOURCE: return eth->regs.int_source;
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case ETH_INT_SOURCE: return eth->regs.int_source;
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case ETH_INT_MASK: return eth->regs.int_mask;
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case ETH_INT_MASK: return eth->regs.int_mask;
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Line 693... |
Line 692... |
*/
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*/
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void eth_write32( oraddr_t addr, uint32_t value, void *dat )
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void eth_write32( oraddr_t addr, uint32_t value, void *dat )
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
addr -= eth->baseaddr;
|
|
|
|
switch( addr ) {
|
switch( addr ) {
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case ETH_MODER:
|
case ETH_MODER:
|
|
|
if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
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if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
|
TEST_FLAG( value, ETH_MODER, RXEN) )
|
TEST_FLAG( value, ETH_MODER, RXEN) )
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Line 887... |
Line 884... |
}
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}
|
|
|
void eth_sec_end(void *dat)
|
void eth_sec_end(void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
struct mem_ops ops;
|
|
|
if(!eth->enabled) {
|
if(!eth->enabled) {
|
free(dat);
|
free(dat);
|
return;
|
return;
|
}
|
}
|
|
|
register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, 0, eth_read32, eth_write32, dat );
|
memset(&ops, 0, sizeof(struct mem_ops));
|
|
|
|
ops.readfunc32 = eth_read32;
|
|
ops.writefunc32 = eth_write32;
|
|
ops.read_dat32 = dat;
|
|
ops.write_dat32 = dat;
|
|
|
|
/* FIXME: Correct delay? */
|
|
ops.delayr = 2;
|
|
ops.delayw = 2;
|
|
reg_mem_area( eth->baseaddr, ETH_ADDR_SPACE, 0, &ops );
|
reg_sim_stat( eth_status, dat );
|
reg_sim_stat( eth_status, dat );
|
reg_sim_reset( eth_reset, dat );
|
reg_sim_reset( eth_reset, dat );
|
}
|
}
|
|
|
void reg_ethernet_sec(void)
|
void reg_ethernet_sec(void)
|