Line 77... |
Line 77... |
#define ETH_MODER_NOPRE_OFFSET 2
|
#define ETH_MODER_NOPRE_OFFSET 2
|
#define ETH_MODER_TXEN_OFFSET 1
|
#define ETH_MODER_TXEN_OFFSET 1
|
#define ETH_MODER_RXEN_OFFSET 0
|
#define ETH_MODER_RXEN_OFFSET 0
|
|
|
/* Field definitions for INT_SOURCE */
|
/* Field definitions for INT_SOURCE */
|
|
#define ETH_INT_SOURCE_RXC_OFFSET 6
|
|
#define ETH_INT_SOURCE_TXC_OFFSET 5
|
#define ETH_INT_SOURCE_BUSY_OFFSET 4
|
#define ETH_INT_SOURCE_BUSY_OFFSET 4
|
#define ETH_INT_SOURCE_RXF_OFFSET 3
|
#define ETH_INT_SOURCE_RXE_OFFSET 3
|
#define ETH_INT_SOURCE_RXB_OFFSET 2
|
#define ETH_INT_SOURCE_RXB_OFFSET 2
|
#define ETH_INT_SOURCE_TXE_OFFSET 1
|
#define ETH_INT_SOURCE_TXE_OFFSET 1
|
#define ETH_INT_SOURCE_TXB_OFFSET 0
|
#define ETH_INT_SOURCE_TXB_OFFSET 0
|
|
|
/* Field definitions for INT_MASK */
|
/* Field definitions for INT_MASK */
|
|
#define ETH_INT_MASK_RXC_M_OFFSET 6
|
|
#define ETH_INT_MASK_TXC_M_OFFSET 5
|
#define ETH_INT_MASK_BUSY_M_OFFSET 4
|
#define ETH_INT_MASK_BUSY_M_OFFSET 4
|
#define ETH_INT_MASK_RXF_M_OFFSET 3
|
#define ETH_INT_MASK_RXE_M_OFFSET 3
|
#define ETH_INT_MASK_RXB_M_OFFSET 2
|
#define ETH_INT_MASK_RXB_M_OFFSET 2
|
#define ETH_INT_MASK_TXE_M_OFFSET 1
|
#define ETH_INT_MASK_TXE_M_OFFSET 1
|
#define ETH_INT_MASK_TXB_M_OFFSET 0
|
#define ETH_INT_MASK_TXB_M_OFFSET 0
|
|
|
/* Field definitions for PACKETLEN */
|
/* Field definitions for PACKETLEN */
|
Line 108... |
Line 112... |
#define ETH_CMODER_TXFLOW_OFFSET 2
|
#define ETH_CMODER_TXFLOW_OFFSET 2
|
#define ETH_CMODER_RXFLOW_OFFSET 1
|
#define ETH_CMODER_RXFLOW_OFFSET 1
|
#define ETH_CMODER_PASSALL_OFFSET 0
|
#define ETH_CMODER_PASSALL_OFFSET 0
|
|
|
/* Field definitions for MIIMODER */
|
/* Field definitions for MIIMODER */
|
#define ETH_MIIMODER_MRST_OFFSET 10
|
#define ETH_MIIMODER_MRST_OFFSET 9
|
#define ETH_MIIMODER_NOPRE_OFFSET 8
|
#define ETH_MIIMODER_NOPRE_OFFSET 8
|
#define ETH_MIIMODER_CLKDIV_OFFSET 0
|
#define ETH_MIIMODER_CLKDIV_OFFSET 0
|
#define ETH_MIIMODER_CLKDIV_WIDTH 8
|
#define ETH_MIIMODER_CLKDIV_WIDTH 8
|
|
|
/* Field definitions for MIICOMMAND */
|
/* Field definitions for MIICOMMAND */
|
Line 125... |
Line 129... |
#define ETH_MIIADDR_RGAD_WIDTH 5
|
#define ETH_MIIADDR_RGAD_WIDTH 5
|
#define ETH_MIIADDR_FIAD_OFFSET 0
|
#define ETH_MIIADDR_FIAD_OFFSET 0
|
#define ETH_MIIADDR_FIAD_WIDTH 5
|
#define ETH_MIIADDR_FIAD_WIDTH 5
|
|
|
/* Field definitions for MIISTATUS */
|
/* Field definitions for MIISTATUS */
|
#define ETH_MIISTAT_NVALID_OFFSET 9
|
#define ETH_MIISTAT_NVALID_OFFSET 1
|
#define ETH_MIISTAT_BUSY_OFFSET 8
|
#define ETH_MIISTAT_BUSY_OFFSET 1
|
#define ETH_MIISTAT_FAIL_OFFSET 0
|
#define ETH_MIISTAT_FAIL_OFFSET 0
|
|
|
/* Field definitions for TX buffer descriptors */
|
/* Field definitions for TX buffer descriptors */
|
#define ETH_TX_BD_LENGTH_OFFSET 16
|
#define ETH_TX_BD_LENGTH_OFFSET 16
|
#define ETH_TX_BD_LENGTH_WIDTH 16
|
#define ETH_TX_BD_LENGTH_WIDTH 16
|