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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [mc.c] - Diff between revs 1461 and 1486

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Rev 1461 Rev 1486
Line 41... Line 41...
#include "mc.h"
#include "mc.h"
#include "abstract.h"
#include "abstract.h"
#include "sim-config.h"
#include "sim-config.h"
#include "debug.h"
#include "debug.h"
 
 
extern struct dev_memarea *dev_list;
struct mc_area {
 
  struct dev_memarea *mem;
 
  unsigned int cs;
 
  int mc;
 
  struct mc_area *next;
 
};
 
 
 
struct mc {
 
  unsigned long csr;
 
  unsigned long poc;
 
  unsigned long ba_mask;
 
  unsigned long csc[N_CE];
 
  unsigned long tms[N_CE];
 
  oraddr_t baseaddr;
 
  int enabled;
 
 
 
  /* Index of this memory controler amongst all the memory controlers */
 
  int index;
 
  /* List of memory devices under this mc's control */
 
  struct mc_area *mc_areas;
 
 
 
  struct mc *next;
 
};
 
 
 
static struct mc *mcs = NULL;
 
 
 
/* List used to temporarily hold memory areas registered with the mc, while the
 
 * mc configureation has not been loaded */
 
static struct mc_area *mc_areas = NULL;
 
 
void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc) {
void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc)
  struct dev_memarea *mem_dev = dev_list;
{
 
  struct mc_area *cur = mc->mc_areas;
 
 
  while (mem_dev) {
  while (cur) {
    if (mem_dev->chip_select == cs) {
    if (cur->cs == cs) {
      mem_dev->addr_mask = mc->ba_mask << 22;
      /* FIXME: No peripheral should _ever_ acess a dev_memarea structure
      mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
       * directly */
      mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
      cur->mem->addr_mask = mc->ba_mask << 22;
 
      cur->mem->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
 
      set_mem_valid(cur->mem, (csc >> MC_CSC_EN_OFFSET) & 0x01);
 
 
      if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
      if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
        mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
        adjust_rw_delay(cur->mem, (tms & 0xff) + ((tms >> 8) & 0x0f),
        mem_dev->delayw = ((tms >> 12)  & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
                        ((tms >> 12)  & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f));
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
        mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
        adjust_rw_delay(cur->mem, 3 + ((tms >> 4) & 0x03),
        mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
                        3 + ((tms >> 4) & 0x03));
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
        mem_dev->delayr = 2;
        adjust_rw_delay(cur->mem, 2, 2);
        mem_dev->delayw = 2;
 
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
        mem_dev->delayr = 2;
        adjust_rw_delay(cur->mem, 2, 2);
        mem_dev->delayw = 2;
 
      }
      }
      return;
      return;
    }
    }
    mem_dev = mem_dev->next;
    cur = cur->next;
  }
  }
}
}
 
 
/* Set a specific MC register with value. */
/* Set a specific MC register with value. */
void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
Line 79... Line 108...
    struct mc *mc = dat;
    struct mc *mc = dat;
        int chipsel;
        int chipsel;
 
 
        debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
        debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
 
 
  addr -= mc->baseaddr;
 
 
 
        switch (addr) {
        switch (addr) {
          case MC_CSR:
          case MC_CSR:
            mc->csr = value;
            mc->csr = value;
            break;
            break;
          case MC_POC:
          case MC_POC:
Line 116... Line 143...
    struct mc *mc = dat;
    struct mc *mc = dat;
        uint32_t value = 0;
        uint32_t value = 0;
 
 
        debug(5, "mc_read_word(%"PRIxADDR")", addr);
        debug(5, "mc_read_word(%"PRIxADDR")", addr);
 
 
  addr -= mc->baseaddr;
 
 
 
        switch (addr) {
        switch (addr) {
          case MC_CSR:
          case MC_CSR:
            value = mc->csr;
            value = mc->csr;
            break;
            break;
          case MC_POC:
          case MC_POC:
Line 147... Line 172...
 
 
/* Read POC register and init memory controler regs. */
/* Read POC register and init memory controler regs. */
void mc_reset(void *dat)
void mc_reset(void *dat)
{
{
  struct mc *mc = dat;
  struct mc *mc = dat;
  struct dev_memarea *mem_dev = dev_list;
  struct mc_area *cur, *prev, *tmp;
 
 
  PRINTF("Resetting memory controller.\n");
  PRINTF("Resetting memory controller.\n");
 
 
  memset(mc->csc, 0, sizeof(mc->csc));
  memset(mc->csc, 0, sizeof(mc->csc));
  memset(mc->tms, 0, sizeof(mc->tms));
  memset(mc->tms, 0, sizeof(mc->tms));
Line 170... Line 195...
    mc->tms[0] = MC_TMS_SSRAM_VALID;
    mc->tms[0] = MC_TMS_SSRAM_VALID;
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
    mc->tms[0] = MC_TMS_SYNC_VALID;
    mc->tms[0] = MC_TMS_SYNC_VALID;
  }
  }
 
 
  while (mem_dev) {
  /* Grab control over all the devices we are destined to control */
    mem_dev->valid = 0;
  cur = mc_areas;
    mem_dev = mem_dev->next;
  prev = NULL;
 
  while (cur) {
 
    if (cur->mc == mc->index) {
 
      if (prev) prev->next = cur->next;
 
      else mc_areas = cur->next;
 
      prev = cur;
 
      tmp = cur->next;
 
      cur->next = mc->mc_areas;
 
      mc->mc_areas = cur;
 
      cur = tmp;
 
    } else {
 
      prev = cur;
 
      cur = cur->next;
  }
  }
 
  }
 
 
 
  for (cur = mc->mc_areas; cur; cur = cur->next)
 
    set_mem_valid(cur->mem, 0);
 
 
  set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
  set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
}
}
 
 
void mc_status(void *dat)
void mc_status(void *dat)
Line 194... Line 235...
        PRINTF( "CE %02d -  CSC: 0x%08lX  TMS: 0x%08lX\n", i, mc->csc[i],
        PRINTF( "CE %02d -  CSC: 0x%08lX  TMS: 0x%08lX\n", i, mc->csc[i],
               mc->tms[i]);
               mc->tms[i]);
    }
    }
}
}
 
 
/*-----------------------------------------------------[ MC configuration }---*/
/*--------------------------------------------[ Peripheral<->MC interface ]---*/
 
/* Registers some memory to be under the memory controllers control */
 
void mc_reg_mem_area(struct dev_memarea *mem, unsigned int cs, int mc)
 
{
 
  struct mc_area *new;
 
 
 
  if(!(new = malloc(sizeof(struct mc_area)))) {
 
    fprintf(stderr, "Out-of-memory\n");
 
    exit(-1);
 
  }
 
  new->cs = cs;
 
  new->mem = mem;
 
  new->mc = mc;
 
 
 
  new->next = mc_areas;
 
  mc_areas = new;
 
}
 
 
 
/*-----------------------------------------------------[ MC configuration ]---*/
void mc_enabled(union param_val val, void *dat)
void mc_enabled(union param_val val, void *dat)
{
{
  struct mc *mc = dat;
  struct mc *mc = dat;
  mc->enabled = val.int_val;
  mc->enabled = val.int_val;
}
}
Line 213... Line 272...
{
{
  struct mc *mc = dat;
  struct mc *mc = dat;
  mc->poc = val.int_val;
  mc->poc = val.int_val;
}
}
 
 
 
void mc_index(union param_val val, void *dat)
 
{
 
  struct mc *mc = dat;
 
  mc->index = val.int_val;
 
}
 
 
void *mc_sec_start(void)
void *mc_sec_start(void)
{
{
  struct mc *new = malloc(sizeof(struct mc));
  struct mc *new = malloc(sizeof(struct mc));
 
 
  if(!new) {
  if(!new) {
    fprintf(stderr, "Peripheral MC: Run out of memory\n");
    fprintf(stderr, "Peripheral MC: Run out of memory\n");
    exit(-1);
    exit(-1);
  }
  }
 
 
 
  new->index = 0;
  new->enabled = 0;
  new->enabled = 0;
 
  new->mc_areas = NULL;
 
 
  return new;
  return new;
}
}
 
 
void mc_sec_end(void *dat)
void mc_sec_end(void *dat)
{
{
  struct mc *mc = dat;
  struct mc *mc = dat;
 
  struct mem_ops ops;
 
 
  if(!mc->enabled) {
  if(!mc->enabled) {
    free(dat);
    free(dat);
    return;
    return;
  }
  }
 
 
  register_memoryarea(mc->baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word,
  /* FIXME: Check to see that the index given to this mc is unique */
                      mc_write_word, dat);
 
 
  mc->next = mcs;
 
  mcs = mc;
 
 
 
  memset(&ops, 0, sizeof(struct mem_ops));
 
 
 
  ops.readfunc32 = mc_read_word;
 
  ops.writefunc32 = mc_write_word;
 
  ops.write_dat32 = dat;
 
  ops.read_dat32 = dat;
 
 
 
  /* FIXME: Correct delays? */
 
  ops.delayr = 2;
 
  ops.delayw = 2;
 
 
 
  reg_mem_area(mc->baseaddr, MC_ADDR_SPACE, 1, &ops);
  reg_sim_reset(mc_reset, dat);
  reg_sim_reset(mc_reset, dat);
  reg_sim_stat(mc_status, dat);
  reg_sim_stat(mc_status, dat);
}
}
 
 
void reg_mc_sec(void)
void reg_mc_sec(void)
Line 249... Line 332...
  struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
  struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
 
 
  reg_config_param(sec, "enabled", paramt_int, mc_enabled);
  reg_config_param(sec, "enabled", paramt_int, mc_enabled);
  reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
  reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
  reg_config_param(sec, "POC", paramt_int, mc_POC);
  reg_config_param(sec, "POC", paramt_int, mc_POC);
 
  reg_config_param(sec, "index", paramt_int, mc_index);
}
}
 
 
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