| Line 33... |
Line 33... |
#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_CSC(i) (0x10 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_TMS(i) (0x14 + (i) * 8)
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#define MC_ADDR_SPACE (MC_CSC(N_CE))
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#define MC_ADDR_SPACE (MC_CSC(N_CE))
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/* POC register field definition */
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#define MC_POC_EN_BW_OFFSET 0
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#define MC_POC_EN_BW_WIDTH 2
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#define MC_POC_EN_MEMTYPE_OFFSET 2
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#define MC_POC_EN_MEMTYPE_WIDTH 2
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/* CSC register field definition */
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/* CSC register field definition */
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#define MC_CSC_EN_OFFSET 0
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#define MC_CSC_EN_OFFSET 0
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#define MC_CSC_MEMTYPE_OFFSET 1
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#define MC_CSC_MEMTYPE_OFFSET 1
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#define MC_CSC_MEMTYPE_WIDTH 2
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#define MC_CSC_MEMTYPE_WIDTH 2
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#define MC_CSC_BW_OFFSET 4
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#define MC_CSC_BW_OFFSET 4
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| Line 48... |
Line 54... |
#define MC_CSC_KRO_OFFSET 10
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#define MC_CSC_KRO_OFFSET 10
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#define MC_CSC_PEN_OFFSET 11
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#define MC_CSC_PEN_OFFSET 11
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#define MC_CSC_SEL_OFFSET 16
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#define MC_CSC_SEL_OFFSET 16
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#define MC_CSC_SEL_WIDTH 8
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#define MC_CSC_SEL_WIDTH 8
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#define MC_CSC_MEMTYPE_SDRAM 0
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#define MC_CSC_MEMTYPE_SSRAM 1
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#define MC_CSC_MEMTYPE_ASYNC 2
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#define MC_CSC_MEMTYPE_SYNC 3
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#define MC_CSR_VALID 0xFF000703LU
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#define MC_CSR_VALID 0xFF000703LU
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#define MC_POC_VALID 0x000000FFLU
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#define MC_POC_VALID 0x0000000FLU
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#define MC_BA_MASK_VALID 0x000000FFLU
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#define MC_BA_MASK_VALID 0x000000FFLU
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#define MC_CSC_VALID 0x00FF0FFFLU
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#define MC_CSC_VALID 0x00FF0FFFLU
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#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
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#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
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#define MC_TMS_SSRAM_VALID 0x00000000LU
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#define MC_TMS_SSRAM_VALID 0x00000000LU
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#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
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#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
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