URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [sim-config.c] - Diff between revs 1486 and 1506

Rev 1486	Rev 1506
Line 250...	Line 250...
`PRINTF("interactive prompt off\n");`	`PRINTF("interactive prompt off\n");`

`PRINTF("Machine initialization...\n");`	`PRINTF("Machine initialization...\n");`
`generate_time_pretty (temp, config.sim.clkcycle_ps);`	`generate_time_pretty (temp, config.sim.clkcycle_ps);`
`PRINTF("Clock cycle: %s\n", temp);`	`PRINTF("Clock cycle: %s\n", temp);`
`if (testsprbits(SPR_UPR, SPR_UPR_DCP))`	`if (cpu_state.sprs[SPR_UPR] & SPR_UPR_DCP)`
`PRINTF("Data cache present.\n");`	`PRINTF("Data cache present.\n");`
`else`	`else`
`PRINTF("No data cache.\n");`	`PRINTF("No data cache.\n");`
`if (testsprbits(SPR_UPR, SPR_UPR_ICP))`	`if (cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP)`
`PRINTF("Insn cache tag present.\n");`	`PRINTF("Insn cache tag present.\n");`
`else`	`else`
`PRINTF("No instruction cache.\n");`	`PRINTF("No instruction cache.\n");`
`if (config.bpb.enabled)`	`if (config.bpb.enabled)`
`PRINTF("BPB simulation on.\n");`	`PRINTF("BPB simulation on.\n");`