URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [default.ld] - Diff between revs 956 and 970

Rev 956	Rev 970
Line 1...	Line 1...
`MEMORY`	`MEMORY`
`{`	`{`
`except : ORIGIN = 0x00000000, LENGTH = 0x00002000`	`except : ORIGIN = 0x00000000, LENGTH = 0x00002000`
`flash : ORIGIN = 0x00002000, LENGTH = 0x001fe000`	`flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000`
`ram : ORIGIN = 0x40000000, LENGTH = 0x00200000`	`ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000`
`}`	`}`

`SECTIONS`	`SECTIONS`
`{`	`{`
	`.text :`
	`{`
	`*(.text)`
	`*(.rodata)`
	`_src_beg = .;`
	`} > flash`
	`.dummy ALIGN(0x4):`
	`{`
	`_src_beg = .;`
	`} > flash`
`.except :`	`.except :`
	`AT ( ADDR (.dummy))`
`{`	`{`
	`_except_beg = .;`
`*(.except)`	`*(.except)`
`_src_beg = .;`	`_except_end = .;`
`} > except`	`} > except`
`.text :`
`AT ( ADDR (.except) + SIZEOF (.except) )`
`{`
`_dst_beg = .;`
`*(.text)`
`} > ram`
`.data :`	`.data :`
`AT ( ADDR (.except) + SIZEOF (.except) + SIZEOF (.text))`	`AT ( ADDR (.dummy) + SIZEOF (.except))`
`{`	`{`
	`_dst_beg = .;`
`*(.data)`	`*(.data)`
`} > ram`
`.rodata :`
`AT ( ADDR (.except) + SIZEOF (.except) + SIZEOF (.text) + SIZEOF (.data))`
`{`
`*(.rodata)`
`_dst_end = .;`	`_dst_end = .;`
`} > ram`	`} > ram`
`.bss :`	`.bss :`
`{`	`{`
`*(.bss)`	`*(.bss)`