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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [except_test_s.S] - Diff between revs 522 and 600

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Rev 522	Rev 600
Line 30...	Line 30...
`.extern _reset_support`	`.extern _reset_support`
`.extern _c_reset`	`.extern _c_reset`
`.extern _excpt_buserr`	`.extern _excpt_buserr`
`.extern _excpt_dpfault`	`.extern _excpt_dpfault`
`.extern _excpt_ipfault`	`.extern _excpt_ipfault`
`.extern _excpt_lpint`	`.extern _excpt_tick`
`.extern _excpt_align`	`.extern _excpt_align`
`.extern _excpt_illinsn`	`.extern _excpt_illinsn`
`.extern _excpt_hpint`	`.extern _excpt_int`
`.extern _excpt_dtlbmiss`	`.extern _excpt_dtlbmiss`
`.extern _excpt_itlbmiss`	`.extern _excpt_itlbmiss`
`.extern _excpt_range`	`.extern _excpt_range`
`.extern _excpt_syscall`	`.extern _excpt_syscall`
`.extern _excpt_break`	`.extern _excpt_break`
Line 187...	Line 187...
`l.lwz r10,0(r10)`	`l.lwz r10,0(r10)`
`l.jr r10`	`l.jr r10`
`l.nop`	`l.nop`

`.org 0x500`	`.org 0x500`
`_lpint_vector:`	`_tick_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.jal store_regs`
`l.nop`	`l.nop`

Line 205...	Line 205...
`l.ori r4,r4,lo(_except_ea)`	`l.ori r4,r4,lo(_except_ea)`
`l.sw 0(r4),r3`	`l.sw 0(r4),r3`

`l.movhi r9,hi(end_except)`	`l.movhi r9,hi(end_except)`
`l.ori r9,r9,lo(end_except)`	`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_lpint)`	`l.movhi r10,hi(_excpt_tick)`
`l.ori r10,r10,lo(_excpt_lpint)`	`l.ori r10,r10,lo(_excpt_tick)`
`l.lwz r10,0(r10)`	`l.lwz r10,0(r10)`
`l.jr r10`	`l.jr r10`
`l.nop`	`l.nop`

`.org 0x600`	`.org 0x600`
Line 262...	Line 262...
`l.lwz r10,0(r10)`	`l.lwz r10,0(r10)`
`l.jr r10`	`l.jr r10`
`l.nop`	`l.nop`

`.org 0x800`	`.org 0x800`
`_hpint_vector:`	`_int_vector:`
`l.addi r1,r1,-116`	`l.addi r1,r1,-116`
`l.sw 0x18(r1),r9`	`l.sw 0x18(r1),r9`
`l.jal store_regs`	`l.jal store_regs`
`l.nop`	`l.nop`

Line 280...	Line 280...
`l.ori r4,r4,lo(_except_ea)`	`l.ori r4,r4,lo(_except_ea)`
`l.sw 0(r4),r3`	`l.sw 0(r4),r3`

`l.movhi r9,hi(end_except)`	`l.movhi r9,hi(end_except)`
`l.ori r9,r9,lo(end_except)`	`l.ori r9,r9,lo(end_except)`
`l.movhi r10,hi(_excpt_hpint)`	`l.movhi r10,hi(_excpt_int)`
`l.ori r10,r10,lo(_excpt_hpint)`	`l.ori r10,r10,lo(_excpt_int)`
`l.lwz r10,0(r10)`	`l.lwz r10,0(r10)`
`l.jr r10`	`l.jr r10`
`l.nop`	`l.nop`

`.org 0x900`	`.org 0x900`
Line 375...	Line 375...
`l.movhi r5,hi(_sys1)`	`l.movhi r5,hi(_sys1)`
`l.ori r5,r5,lo(_sys1)`	`l.ori r5,r5,lo(_sys1)`
`l.sub r5,r4,r5`	`l.sub r5,r4,r5`

`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`	`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
`l.ori r4,r4,1`	`l.ori r4,r4,SPR_SR_SM`
`l.mtspr r0,r4,SPR_ESR_BASE`	`l.mtspr r0,r4,SPR_ESR_BASE`

`l.movhi r4,hi(_sys2)`	`l.movhi r4,hi(_sys2)`
`l.ori r4,r4,lo(_sys2)`	`l.ori r4,r4,lo(_sys2)`
`l.mtspr r0,r4,SPR_EPCR_BASE`	`l.mtspr r0,r4,SPR_EPCR_BASE`
Line 509...	Line 509...
`_except_basic:`	`_except_basic:`
`_sys1:`	`_sys1:`
`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`	`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
`l.mfspr r4,r0,SPR_SR`	`l.mfspr r4,r0,SPR_SR`
`l.and r4,r4,r3`	`l.and r4,r4,r3`
`l.ori r4,r4,6`	`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
`l.mtspr r0,r4,SPR_SR`	`l.mtspr r0,r4,SPR_SR`

`l.addi r3,r0,0`	`l.addi r3,r0,0`
`l.sys 1`	`l.sys 1`
`l.addi r3,r3,2`	`l.addi r3,r3,2`

`_sys2:`	`_sys2:`
`l.addi r11,r0,0`	`l.addi r11,r0,0`

`l.mfspr r4,r0,SPR_SR /* Check SR */`	`l.mfspr r4,r0,SPR_SR /* Check SR */`
`l.andi r4,r4,7`	`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
`l.sfeqi r4,7`	`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
`l.bf 1f`	`l.bf 1f`
`l.nop`	`l.nop`
`l.addi r11,r11,1`	`l.addi r11,r11,1`
`1:`	`1:`
`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`	`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`
Line 536...	Line 536...
`l.sfeqi r5,0x1c /* Check the EPCR */`	`l.sfeqi r5,0x1c /* Check the EPCR */`
`l.bf 1f`	`l.bf 1f`
`l.nop`	`l.nop`
`l.addi r11,r11,4`	`l.addi r11,r11,4`
`1:`	`1:`
`l.sfeqi r6,3 /* Check the SR when exception is taken */`	`l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */`
`l.bf 1f`	`l.bf 1f`
`l.nop`	`l.nop`
`l.addi r11,r11,8`	`l.addi r11,r11,8`
`1:`	`1:`
`l.jr r9`	`l.jr r9`
`l.nop`	`l.nop`

`_lo_dmmu_en:`	`_lo_dmmu_en:`
`l.mfspr r3,r0,SPR_SR`	`l.mfspr r3,r0,SPR_SR`
`l.ori r3,r3,SPR_SR_EXR`
`l.ori r3,r3,SPR_SR_DME`	`l.ori r3,r3,SPR_SR_DME`
`l.mtspr r0,r3,SPR_ESR_BASE`	`l.mtspr r0,r3,SPR_ESR_BASE`
`l.mtspr r0,r9,SPR_EPCR_BASE`	`l.mtspr r0,r9,SPR_EPCR_BASE`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`

`_lo_immu_en:`	`_lo_immu_en:`
`l.mfspr r3,r0,SPR_SR`	`l.mfspr r3,r0,SPR_SR`
`l.ori r3,r3,SPR_SR_EXR`
`l.ori r3,r3,SPR_SR_IME`	`l.ori r3,r3,SPR_SR_IME`
`l.mtspr r0,r3,SPR_ESR_BASE`	`l.mtspr r0,r3,SPR_ESR_BASE`
`l.mtspr r0,r9,SPR_EPCR_BASE`	`l.mtspr r0,r9,SPR_EPCR_BASE`
`l.rfe`	`l.rfe`
`l.nop`	`l.nop`
Line 569...	Line 567...
`l.jr r3`	`l.jr r3`
`l.nop`	`l.nop`

`_call_with_int:`	`_call_with_int:`
`l.mfspr r8,r0,SPR_SR`	`l.mfspr r8,r0,SPR_SR`
`l.ori r8,r8,SPR_SR_EIR`	`l.ori r8,r8,SPR_SR_TEE`
`l.mtspr r0,r8,SPR_ESR_BASE`	`l.mtspr r0,r8,SPR_ESR_BASE`
`l.mtspr r0,r3,SPR_EPCR_BASE`	`l.mtspr r0,r3,SPR_EPCR_BASE`
`l.rfe`	`l.rfe`

`_load_acc_32:`	`_load_acc_32:`
Line 623...	Line 621...
`l.nop`	`l.nop`

`_int_trigger:`	`_int_trigger:`
`l.addi r11,r0,0`	`l.addi r11,r0,0`
`l.mfspr r3,r0,SPR_SR`	`l.mfspr r3,r0,SPR_SR`
`l.ori r3,r3,SPR_SR_EIR`	`l.ori r3,r3,SPR_SR_TEE`
`l.mtspr r0,r3,SPR_SR`	`l.mtspr r0,r3,SPR_SR`
`l.addi r11,r11,1`	`l.addi r11,r11,1`

`_int_loop:`	`_int_loop:`
`l.j _int_loop`	`l.j _int_loop`

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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [except_test_s.S] - Diff between revs 522 and 600