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/* sim.cfg -- Simulator configuration script file
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Copyright (C) 2001, Marko Mlinar, markom@opencores.org
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This file includes a lot of help about configurations and default one
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* INTRODUCTION
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The or1ksim have various parameters, which can be set in configuration
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files. Multiple configurations may be used and switched between at
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or1ksim startup.
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By default, or1ksim loads condfiguration file from './sim.cfg' and if not
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found it checks '~/.or1k/sim.cfg'. If even this file is not found or
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all parameters are not defined, default configuration is used.
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Users should not rely on default configuration, but rather redefine all
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critical settings, since default configuration may differ in newer
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versions of the or1ksim.
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If multiple configurations are used, user can switch between them by
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supplying -f option when starting simulator.
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This file may contain (standard C) only comments - no // support.
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Like normal configuration file, this file is divided in sections,
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where each section is described in detail also.
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Some section also have subsections. One example of such subsection is
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block:
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device
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instance specific parameters...
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enddevice
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which creates a device instance.
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*/
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/* MEMORY SECTION
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This section specifies how is initial memory generated and which blocks
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it consist of.
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type = random/unknown/pattern
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specifies the initial memory values. 'random' parameter generate
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random memory using seed 'random_seed' parameter. 'pattern' parameter
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fills memory with 'pattern' parameter and 'unknown' does not specify
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how memory should be generated - the fastest option.
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random_seed =
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random seed for randomizer, used if type = random
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pattern =
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pattern to fill memory, used if type = pattern
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nmemories =
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number of memory instances connected
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instance specific:
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baseaddr =
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memory start address
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size =
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memory size
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name = ""
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memory block name
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ce =
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chip enable index of the memory instance
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delayr =
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cycles, required for read access, -1 if instance does not support reading
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delayw =
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cycles, required for write access, -1 if instance does not support writing
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16550 = 0/1
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0, if this device is uart 16450 and 1, if it is 16550
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log = ""
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filename, where to log memory accesses to, no log, if log command is not specified
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*/
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section memory
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section memory
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/*random_seed = 12345
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/*random_seed = 12345
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type = random*/
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type = random*/
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pattern = 0x00
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pattern = 0x00
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type = unknown /* Fastest */
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type = unknown /* Fastest */
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delayr = 10
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delayr = 10
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delayw = -1
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delayw = -1
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enddevice
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enddevice
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end
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end
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/* IMMU SECTION
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This section configures Instruction Memory Menangement Unit
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enabled = 0/1
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whether IMMU is enabled
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(NOTE: UPR bit is set)
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nsets =
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number of ITLB sets; must be power of two
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nways =
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number of ITLB ways
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pagesize =
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instruction page size; must be power of two
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entrysize =
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instruction entry size in bytes
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ustates =
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number of ITLB usage states (2, 3, 4 etc., max is 4)
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*/
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section immu
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section immu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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ustates = 2
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ustates = 2
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pagesize = 8192
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pagesize = 8192
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end
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end
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/* DMMU SECTION
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This section configures Data Memory Menangement Unit
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enabled = 0/1
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whether DMMU is enabled
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(NOTE: UPR bit is set)
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nsets =
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number of DTLB sets; must be power of two
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nways =
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number of DTLB ways
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pagesize =
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data page size; must be power of two
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entrysize =
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data entry size in bytes
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ustates =
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number of DTLB usage states (2, 3, 4 etc., max is 4)
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*/
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section dmmu
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section dmmu
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enabled = 1
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enabled = 1
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nsets = 64
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nsets = 64
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nways = 1
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nways = 1
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ustates = 2
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ustates = 2
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pagesize = 8192
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pagesize = 8192
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end
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end
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/* IC SECTION
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This section configures Instruction Cache
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enabled = 0/1
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whether IC is enabled
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(NOTE: UPR bit is set)
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nsets =
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number of IC sets; must be power of two
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nways =
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number of IC ways
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blocksize =
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IC block size in bytes; must be power of two
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ustates =
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number of IC usage states (2, 3, 4 etc., max is 4)
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*/
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section ic
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section ic
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enabled = 1
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enabled = 1
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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ustates = 2
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ustates = 2
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blocksize = 16
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blocksize = 16
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end
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end
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/* DC SECTION
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This section configures Data Cache
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enabled = 0/1
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whether DC is enabled
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(NOTE: UPR bit is set)
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nsets =
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number of DC sets; must be power of two
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nways =
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number of DC ways
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blocksize =
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DC block size in bytes; must be power of two
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ustates =
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number of DC usage states (2, 3, 4 etc., max is 4)
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*/
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section dc
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section dc
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enabled = 1
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enabled = 1
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nsets = 256
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nsets = 256
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nways = 1
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nways = 1
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ustates = 2
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ustates = 2
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blocksize = 16
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blocksize = 16
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end
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end
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/* SIM SECTION
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This section specifies how should sim behave.
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verbose = 0/1
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whether to print out extra messages
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debug = 0-9
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= 0 disabled debug messages
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1-9 level of sim debug information, greater the number more verbose is
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the output
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profile = 0/1
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whether to generate profiling file 'sim.profile'
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prof_fn = ""
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filename, where to generate profiling info, used
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only if 'profile' is set
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history = 0/1
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whether instruction execution flow is tracked for
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display by simulator hist command. Useful for
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back-trace debugging.
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iprompt = 0/1
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whether we strart in interactive prompt
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exe_log = 0/1
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whether execution log should be generated
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exe_log_fn = ""
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where to put execution log in, used only if 'exe_log'
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is set
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clkcycle = [ps|ns|us|ms]
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specifies time measurement for one cycle
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*/
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section sim
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section sim
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/* verbose = 1 */
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/* verbose = 1 */
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debug = 0
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debug = 0
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profile = 0
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profile = 0
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prof_fn = "sim.profile"
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prof_fn = "sim.profile"
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/* iprompt = 0 */
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/* iprompt = 0 */
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exe_log = 0
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exe_log = 0
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exe_log_fn = "executed.log"
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exe_log_fn = "executed.log"
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end
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end
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/* SECTION VAPI
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This section configures Verification API, used for Advanced
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Core Verification.
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enabled = 0/1
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whether to start VAPI server
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server_port =
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TCP/IP port to start VAPI server on
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log_enabled = 0/1
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whether logging of VAPI requests is enabled
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vapi_fn =
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specifies filename where to log into, if log_enabled is selected
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*/
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section VAPI
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enabled = 0
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server_port = 9998
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log_enabled = 0
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vapi_log_fn = "vapi.log"
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end
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/* CPU SECTION
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This section specifies various CPU parameters.
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ver =
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rev =
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specifies version and revision of the CPU used
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upr =
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changes the upr register
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superscalar = 0/1
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whether CPU is scalar or superscalar
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(modify cpu/or32/execute.c to tune superscalar model)
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hazards = 0/1
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whether data hazards are tracked in superscalar CPU
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and displayed by the simulator r command
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dependstats = 0/1
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whether inter-instruction dependencies are calculated
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and displayed by simulator stats command.
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*/
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section cpu
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ver = 0x1200
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rev = 0x0001
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/* upr = */
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superscalar = 0
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hazards = 0
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dependstats = 0
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end
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section bpb
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enabled = 0
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btic = 0
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end
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/* DEBUG SECTION
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This sections specifies how debug unit should behave.
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enabled = 0/1
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whether debug unit is enabled
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gdb_enabled = 0/1
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whether to start gdb server at 'server_port' port
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server_port =
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TCP/IP port to start gdb server on, used only if gdb_enabled
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is set
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section debug
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enabled = 0
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gdb_enabled = 0
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server_port = 9999
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end
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/* MC SECTION
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This section configures the memory controller
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enabled = 0/1
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whether memory controller is enabled
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baseaddr =
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address of first MC register
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POC =
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Power On Configuration register
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*/
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section mc
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enabled = 0
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baseaddr = 0xa0000000
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POC = 0x00000008 /* Power on configuration register */
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end
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/* TICK TIMER SECTION
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This section configures tick timer
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enabled = 0/1
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whether tick timer is enabled
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irq =
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irq number
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*/
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section tick
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enabled = 0
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irq = 3
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end
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