| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Added a directive to ignore signed division variables that are only used in simulation.
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//
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// Revision 1.5 2002/03/29 16:33:59 lampret
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// Revision 1.5 2002/03/29 16:33:59 lampret
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// Added again just recently removed full_case directive
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// Added again just recently removed full_case directive
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//
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//
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// Revision 1.4 2002/03/29 15:16:53 lampret
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// Revision 1.4 2002/03/29 15:16:53 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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| Line 158... |
Line 161... |
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//
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//
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// Central part of the ALU
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// Central part of the ALU
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//
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//
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
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casex (alu_op) // synopsys parallel_case full_case
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`ifdef OR1200_CASE_DEFAULT
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casex (alu_op) // synopsys parallel_case
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`else
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casex (alu_op) // synopsys full_case parallel_case
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`endif
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`OR1200_ALUOP_SHROT : begin
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`OR1200_ALUOP_SHROT : begin
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result = shifted_rotated;
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result = shifted_rotated;
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end
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end
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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result = result_sum;
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result = result_sum;
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| Line 214... |
Line 221... |
else
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else
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result = 32'h00000000;
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result = 32'h00000000;
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end
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end
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`endif
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`endif
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// synopsys translate_on
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// synopsys translate_on
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
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`ifdef OR1200_CASE_DEFAULT
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default: begin
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`else
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND
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`endif
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result = result_and;
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result = result_and;
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end
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end
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endcase
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endcase
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end
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end
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|
